^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Timberdale FPGA GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Mocean Laboratories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Timberdale FPGA GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/timb_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRIVER_NAME "timb-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TGPIOVAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TGPIODIR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TGPIO_IER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TGPIO_ISR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TGPIO_IPR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TGPIO_ICR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TGPIO_FLR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TGPIO_LVR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TGPIO_VER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TGPIO_BFLR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct timbgpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) spinlock_t lock; /* mutual exclusion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long last_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned offset, bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct timbgpio *tgpio = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) spin_lock(&tgpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = ioread32(tgpio->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reg |= (1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reg &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iowrite32(reg, tgpio->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) spin_unlock(&tgpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct timbgpio *tgpio = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) value = ioread32(tgpio->membase + TGPIOVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return (value & (1 << nr)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void timbgpio_gpio_set(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct timbgpio *tgpio = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (tgpio->irq_base <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return tgpio->irq_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * GPIO IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void timbgpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int offset = d->irq - tgpio->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tgpio->last_ier &= ~(1UL << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_unlock_irqrestore(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void timbgpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int offset = d->irq - tgpio->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_lock_irqsave(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tgpio->last_ier |= 1UL << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock_irqrestore(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int offset = d->irq - tgpio->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 lvr, flr, bflr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (offset < 0 || offset > tgpio->gpio.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ver = ioread32(tgpio->membase + TGPIO_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock_irqsave(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) lvr = ioread32(tgpio->membase + TGPIO_LVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) flr = ioread32(tgpio->membase + TGPIO_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ver > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bflr = ioread32(tgpio->membase + TGPIO_BFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bflr &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) flr &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (trigger & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lvr |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) lvr &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ver < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) flr |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bflr |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bflr &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) flr |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (trigger & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lvr &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) lvr |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) iowrite32(lvr, tgpio->membase + TGPIO_LVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iowrite32(flr, tgpio->membase + TGPIO_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ver > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_unlock_irqrestore(&tgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void timbgpio_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct irq_data *data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) data->chip->irq_ack(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ipr = ioread32(tgpio->membase + TGPIO_IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) iowrite32(ipr, tgpio->membase + TGPIO_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Some versions of the hardware trash the IER register if more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * one interrupt is received simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iowrite32(0, tgpio->membase + TGPIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct irq_chip timbgpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .irq_enable = timbgpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .irq_disable = timbgpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .irq_set_type = timbgpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int timbgpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct timbgpio *tgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!pdata || pdata->nr_pins > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(dev, "Invalid platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!tgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tgpio->irq_base = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_init(&tgpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (IS_ERR(tgpio->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return PTR_ERR(tgpio->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) gc = &tgpio->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) gc->label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) gc->direction_input = timbgpio_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) gc->get = timbgpio_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gc->direction_output = timbgpio_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) gc->set = timbgpio_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) gc->dbg_show = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) gc->base = pdata->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) gc->ngpio = pdata->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) gc->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) platform_set_drvdata(pdev, tgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* make sure to disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) iowrite32(0x0, tgpio->membase + TGPIO_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (irq < 0 || tgpio->irq_base <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; i < pdata->nr_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) irq_set_chip_and_handler(tgpio->irq_base + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) &timbgpio_irqchip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) irq_set_chip_data(tgpio->irq_base + i, tgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct platform_driver timbgpio_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .probe = timbgpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) builtin_platform_driver(timbgpio_platform_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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