^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thierry Reding <treding@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/gpio/tegra186-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/gpio/tegra194-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* security registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA186_GPIO_CTL_SCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA186_GPIO_INPUT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tegra_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct tegra186_pin_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct tegra_gpio_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct tegra_gpio_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct tegra186_pin_range *pin_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int num_pin_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char *pinmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tegra_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct irq_chip intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int num_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct tegra_gpio_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *secure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct tegra_gpio_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int start = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for (i = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct tegra_gpio_port *port = &gpio->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (*pin >= start && *pin < start + port->pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *pin -= start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) start += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct tegra_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) port = tegra186_gpio_get_port(gpio, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) offset = port->bank * 0x1000 + port->port * 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return gpio->base + offset + pin * 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int tegra186_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int tegra186_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int tegra186_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int offset, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* configure output level first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) chip->set(chip, offset, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* set the direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) value = readl(base + TEGRA186_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return value & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (level == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int tegra186_gpio_set_config(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 debounce, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) base = tegra186_gpio_get_base(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (debounce > 255000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pctldev = of_pinctrl_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) const char *group = gpio->soc->pin_ranges[i].group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) port = pin / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pin = pin % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (port >= gpio->soc->num_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_warn(chip->parent, "invalid port %u for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) port, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (j = 0; j < port; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pin += gpio->soc->ports[j].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const struct of_phandle_args *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int port, pin, i, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (WARN_ON(chip->of_gpio_n_cells < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) port = spec->args[0] / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pin = spec->args[0] % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (port >= gpio->soc->num_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(chip->parent, "invalid port number: %u\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = 0; i < port; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) offset += gpio->soc->ports[i].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *flags = spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return offset + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void tegra186_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct tegra_gpio *gpio = to_tegra_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) base = tegra186_gpio_get_base(gpio, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void tegra186_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct tegra_gpio *gpio = to_tegra_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) base = tegra186_gpio_get_base(gpio, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void tegra186_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct tegra_gpio *gpio = to_tegra_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) base = tegra186_gpio_get_base(gpio, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct tegra_gpio *gpio = to_tegra_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) base = tegra186_gpio_get_base(gpio, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (WARN_ON(base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (data->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return irq_chip_set_type_parent(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (data->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return irq_chip_set_wake_parent(data, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void tegra186_gpio_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct irq_domain *domain = gpio->gpio.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int parent = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int i, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (i = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct tegra_gpio_port *port = &gpio->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int pin, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* skip ports that are not associated with this bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (parent != gpio->irq[port->bank])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for_each_set_bit(pin, &value, port->pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) irq = irq_find_mapping(domain, offset + pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (WARN_ON(irq == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) offset += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int port, pin, i, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) port = fwspec->param[0] / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pin = fwspec->param[0] % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (port >= gpio->soc->num_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (i = 0; i < port; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) offset += gpio->soc->ports[i].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *hwirq = offset + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int parent_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct irq_fwspec *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!fwspec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) fwspec->fwnode = chip->irq.parent_domain->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fwspec->param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) fwspec->param[0] = gpio->soc->instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) fwspec->param[1] = parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fwspec->param[2] = parent_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int *parent_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned int *parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *parent_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct tegra_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (offset < gpio->soc->ports[i].pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) offset -= gpio->soc->ports[i].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return offset + i * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct of_device_id tegra186_pmc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { .compatible = "nvidia,tegra186-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { .compatible = "nvidia,tegra194-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const struct tegra_gpio_port *port = &gpio->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int offset, p = port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) base = gpio->secure + port->bank * 0x1000 + 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) value = readl(base + TEGRA186_GPIO_CTL_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * For controllers that haven't been locked down yet, make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * sure to program the default interrupt route mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) value = readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) value = BIT(port->pins) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) writel(value, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int tegra186_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int i, j, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct tegra_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) char **names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) gpio->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (IS_ERR(gpio->secure))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return PTR_ERR(gpio->secure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (IS_ERR(gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return PTR_ERR(gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) err = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) gpio->num_irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!gpio->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0; i < gpio->num_irq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) err = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) gpio->irq[i] = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gpio->gpio.label = gpio->soc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) gpio->gpio.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) gpio->gpio.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gpio->gpio.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) gpio->gpio.get_direction = tegra186_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gpio->gpio.direction_input = tegra186_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) gpio->gpio.direction_output = tegra186_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gpio->gpio.get = tegra186_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gpio->gpio.set = tegra186_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) gpio->gpio.set_config = tegra186_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gpio->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) for (i = 0; i < gpio->soc->num_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) gpio->gpio.ngpio += gpio->soc->ports[i].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) sizeof(*names), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) const struct tegra_gpio_port *port = &gpio->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (j = 0; j < port->pins; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "P%s.%02x", port->name, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) names[offset + j] = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) offset += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) gpio->gpio.names = (const char * const *)names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) gpio->gpio.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) gpio->gpio.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) gpio->intc.name = pdev->dev.of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) gpio->intc.irq_ack = tegra186_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) gpio->intc.irq_mask = tegra186_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) gpio->intc.irq_unmask = tegra186_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) gpio->intc.irq_set_type = tegra186_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) gpio->intc.irq_set_wake = tegra186_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) irq = &gpio->gpio.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) irq->chip = &gpio->intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) irq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) irq->parent_handler = tegra186_gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) irq->parent_handler_data = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) irq->num_parents = gpio->num_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) irq->parents = gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) np = of_find_matching_node(NULL, tegra186_pmc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) irq->parent_domain = irq_find_host(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!irq->parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tegra186_gpio_init_route_mapping(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) sizeof(*irq->map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!irq->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) const struct tegra_gpio_port *port = &gpio->soc->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) for (j = 0; j < port->pins; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) irq->map[offset + j] = irq->parents[port->bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) offset += port->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int tegra186_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .bank = _bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .port = _port, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .pins = _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const struct tegra_gpio_port tegra186_main_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct tegra_gpio_soc tegra186_main_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .num_ports = ARRAY_SIZE(tegra186_main_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .ports = tegra186_main_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "tegra186-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .instance = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [TEGRA186_AON_GPIO_PORT_##_name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .bank = _bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .port = _port, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .pins = _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct tegra_gpio_port tegra186_aon_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const struct tegra_gpio_soc tegra186_aon_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .num_ports = ARRAY_SIZE(tegra186_aon_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .ports = tegra186_aon_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .name = "tegra186-gpio-aon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .instance = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .bank = _bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .port = _port, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .pins = _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const struct tegra_gpio_port tegra194_main_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct tegra_gpio_soc tegra194_main_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .num_ports = ARRAY_SIZE(tegra194_main_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .ports = tegra194_main_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .name = "tegra194-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .instance = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pin_ranges = tegra194_main_pin_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .pinmux = "nvidia,tegra194-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [TEGRA194_AON_GPIO_PORT_##_name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .bank = _bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .port = _port, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .pins = _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct tegra_gpio_port tegra194_aon_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const struct tegra_gpio_soc tegra194_aon_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .num_ports = ARRAY_SIZE(tegra194_aon_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ports = tegra194_aon_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .name = "tegra194-gpio-aon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .instance = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct of_device_id tegra186_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .compatible = "nvidia,tegra186-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .data = &tegra186_main_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .compatible = "nvidia,tegra186-gpio-aon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .data = &tegra186_aon_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .compatible = "nvidia,tegra194-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .data = &tegra194_main_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .compatible = "nvidia,tegra194-gpio-aon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .data = &tegra194_aon_soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static struct platform_driver tegra186_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .name = "tegra186-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .of_match_table = tegra186_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .probe = tegra186_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .remove = tegra186_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) module_platform_driver(tegra186_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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