^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-tegra/gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 Google, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Erik Gilling <konkers@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPIO_BANK(x) ((x) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_PORT(x) (((x) >> 3) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_BIT(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GPIO_PORT(x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIO_INT_LVL_MASK 0x010101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIO_INT_LVL_EDGE_RISING 0x000101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO_INT_LVL_EDGE_FALLING 0x000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO_INT_LVL_EDGE_BOTH 0x010100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO_INT_LVL_LEVEL_LOW 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct tegra_gpio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct tegra_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) spinlock_t lvl_lock[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 cnf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 out[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 oe[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 int_enb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 int_lvl[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 wake_enb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 dbc_enb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 dbc_cnt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra_gpio_info *tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct tegra_gpio_soc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool debounce_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 bank_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 upper_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct tegra_gpio_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct tegra_gpio_bank *bank_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct tegra_gpio_soc_config *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct irq_chip ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 bank_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(val, tgi->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return readl_relaxed(tgi->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int gpio, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val = 0x100 << GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= 1 << GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tegra_gpio_writel(tgi, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return pinctrl_gpio_request(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pinctrl_gpio_free(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tegra_gpio_disable(tgi, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int bval = BIT(GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* If gpio is in output mode then read from the out value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int tegra_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tegra_gpio_enable(tgi, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(tgi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "Failed to set pinctrl input direction of GPIO %d: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chip->base + offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int tegra_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tegra_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tegra_gpio_enable(tgi, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(tgi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Failed to set pinctrl output direction of GPIO %d: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) chip->base + offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int tegra_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 pin_mask = BIT(GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 cnf, oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(cnf & pin_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (oe & pin_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!debounce_ms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) debounce_ms = min(debounce_ms, 255U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) port = GPIO_PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* There is only one debounce count register per port and hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * set the maximum of current and requested debounce time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_irqsave(&bank->dbc_lock[port], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (bank->dbc_cnt[port] < debounce_ms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bank->dbc_cnt[port] = debounce_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return tegra_gpio_set_debounce(chip, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return irq_find_mapping(tgi->irq_domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void tegra_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void tegra_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void tegra_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) lvl_type = GPIO_INT_LVL_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) lvl_type = GPIO_INT_LVL_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) lvl_type = GPIO_INT_LVL_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) lvl_type = GPIO_INT_LVL_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_lock_irqsave(&bank->lvl_lock[port], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val |= lvl_type << GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tegra_gpio_enable(tgi, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(tgi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "unable to lock Tegra GPIO %u as IRQ\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tegra_gpio_disable(tgi, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void tegra_gpio_irq_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tegra_gpio_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gpiochip_unlock_as_irq(&tgi->gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void tegra_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int port, pin, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bool unmasked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned long sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct tegra_gpio_info *tgi = bank->tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (port = 0; port < 4; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gpio = tegra_gpio_compose(bank->bank, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for_each_set_bit(pin, &sta, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tegra_gpio_writel(tgi, 1 << pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GPIO_INT_CLR(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* if gpio is edge triggered, clear condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * before executing the handler so that we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * miss edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!unmasked && lvl & (0x100 << pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unmasked = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) generic_handle_irq(irq_find_mapping(tgi->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) gpio + pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!unmasked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int tegra_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int b, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (b = 0; b < tgi->bank_count; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct tegra_gpio_bank *bank = &tgi->bank_info[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int gpio = (b << 5) | (p << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tegra_gpio_writel(tgi, bank->cnf[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GPIO_CNF(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (tgi->soc->debounce_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tegra_gpio_writel(tgi, bank->dbc_cnt[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GPIO_DBC_CNT(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tegra_gpio_writel(tgi, bank->dbc_enb[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GPIO_MSK_DBC_EN(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tegra_gpio_writel(tgi, bank->out[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GPIO_OUT(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tegra_gpio_writel(tgi, bank->oe[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GPIO_OE(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tegra_gpio_writel(tgi, bank->int_lvl[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GPIO_INT_LVL(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tegra_gpio_writel(tgi, bank->int_enb[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GPIO_INT_ENB(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int tegra_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int b, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (b = 0; b < tgi->bank_count; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct tegra_gpio_bank *bank = &tgi->bank_info[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int gpio = (b << 5) | (p << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) bank->cnf[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GPIO_CNF(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bank->out[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GPIO_OUT(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) bank->oe[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GPIO_OE(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (tgi->soc->debounce_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bank->dbc_enb[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GPIO_MSK_DBC_EN(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bank->dbc_enb[p];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bank->int_enb[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GPIO_INT_ENB(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bank->int_lvl[p] = tegra_gpio_readl(tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GPIO_INT_LVL(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Enable gpio irq for wake up source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tegra_gpio_writel(tgi, bank->wake_enb[p],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GPIO_INT_ENB(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 port, bit, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) err = irq_set_irq_wake(bank->irq, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) port = GPIO_PORT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mask = BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bank->wake_enb[port] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bank->wake_enb[port] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct tegra_gpio_info *tgi = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for (i = 0; i < tgi->bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int gpio = tegra_gpio_compose(i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) seq_printf(s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) i, j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &tegra_dbg_gpio_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct dev_pm_ops tegra_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int tegra_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct tegra_gpio_info *tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct tegra_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int gpio, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!tgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tgi->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tgi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) tgi->bank_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!tgi->bank_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_err(&pdev->dev, "Missing IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) tgi->gc.label = "tegra-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tgi->gc.request = tegra_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) tgi->gc.free = tegra_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) tgi->gc.direction_input = tegra_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) tgi->gc.get = tegra_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tgi->gc.direction_output = tegra_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tgi->gc.set = tegra_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) tgi->gc.get_direction = tegra_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) tgi->gc.to_irq = tegra_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tgi->gc.base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tgi->gc.ngpio = tgi->bank_count * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tgi->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) tgi->gc.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) tgi->ic.name = "GPIO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) tgi->ic.irq_ack = tegra_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) tgi->ic.irq_mask = tegra_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) platform_set_drvdata(pdev, tgi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (tgi->soc->debounce_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tgi->gc.set_config = tegra_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sizeof(*tgi->bank_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!tgi->bank_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tgi->gc.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!tgi->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; i < tgi->bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bank = &tgi->bank_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) bank->bank = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bank->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bank->tgi = tgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tgi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (IS_ERR(tgi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return PTR_ERR(tgi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) for (i = 0; i < tgi->bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int gpio = tegra_gpio_compose(i, j, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) irq_domain_remove(tgi->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int irq = irq_create_mapping(tgi->irq_domain, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* No validity check; all Tegra GPIOs are valid IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bank = &tgi->bank_info[GPIO_BANK(gpio)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) irq_set_chip_data(irq, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; i < tgi->bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) bank = &tgi->bank_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) irq_set_chained_handler_and_data(bank->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) tegra_gpio_irq_handler, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) spin_lock_init(&bank->lvl_lock[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) spin_lock_init(&bank->dbc_lock[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tegra_gpio_debuginit(tgi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct tegra_gpio_soc_config tegra20_gpio_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .bank_stride = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .upper_offset = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct tegra_gpio_soc_config tegra30_gpio_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .bank_stride = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .upper_offset = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct tegra_gpio_soc_config tegra210_gpio_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .debounce_supported = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .bank_stride = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .upper_offset = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const struct of_device_id tegra_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static struct platform_driver tegra_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "tegra-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .pm = &tegra_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .of_match_table = tegra_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .probe = tegra_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int __init tegra_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return platform_driver_register(&tegra_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) subsys_initcall(tegra_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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