Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/tc3589x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * These registers are modified under the irq bus lock and cached to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * unnecessary writes in bus_sync_unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CACHE_NR_REGS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CACHE_NR_BANKS	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct tc3589x_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct tc3589x *tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/* Caches of interrupt control registers for bus_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ret = tc3589x_reg_read(tc3589x, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 					 unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8 reg = TC3589x_GPIODIR0 + offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	tc3589x_gpio_set(chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 reg = TC3589x_GPIODIR0 + offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned int pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				      unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 reg = TC3589x_GPIODIR0 + offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned int pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ret = tc3589x_reg_read(tc3589x, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (ret & BIT(pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				   unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * These registers are alterated at each second address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * ODM bit 0 = drive to GND or Hi-Z (open drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * ODM bit 1 = drive to VDD or Hi-Z (open source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int pos = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		/* Set open drain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/* Enable open drain/source mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		/* Set open source mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* Enable open drain/source mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* Disable open drain/source mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct gpio_chip template_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.label			= "tc3589x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.get			= tc3589x_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.set			= tc3589x_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.direction_output	= tc3589x_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.direction_input	= tc3589x_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.get_direction		= tc3589x_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.set_config		= tc3589x_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.can_sleep		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (type == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void tc3589x_gpio_irq_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mutex_lock(&tc3589x_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	static const u8 regmap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		[REG_IBE]	= TC3589x_GPIOIBE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		[REG_IEV]	= TC3589x_GPIOIEV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		[REG_IS]	= TC3589x_GPIOIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		[REG_IE]	= TC3589x_GPIOIE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		[REG_DIRECT]	= TC3589x_DIRECT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	for (i = 0; i < CACHE_NR_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		for (j = 0; j < CACHE_NR_BANKS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			u8 old = tc3589x_gpio->oldregs[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			u8 new = tc3589x_gpio->regs[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			if (new == old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			tc3589x_gpio->oldregs[i][j] = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			tc3589x_reg_write(tc3589x, regmap[i] + j, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	mutex_unlock(&tc3589x_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void tc3589x_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void tc3589x_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct irq_chip tc3589x_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.name			= "tc3589x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.irq_bus_lock		= tc3589x_gpio_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.irq_mask		= tc3589x_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.irq_unmask		= tc3589x_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.irq_set_type		= tc3589x_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct tc3589x_gpio *tc3589x_gpio = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u8 status[CACHE_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				 ARRAY_SIZE(status), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	for (i = 0; i < ARRAY_SIZE(status); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		unsigned int stat = status[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			int bit = __ffs(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			int line = i * 8 + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 						   line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			handle_nested_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			stat &= ~(1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int tc3589x_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct tc3589x_gpio *tc3589x_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		dev_err(&pdev->dev, "No Device Tree node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (!tc3589x_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	mutex_init(&tc3589x_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	tc3589x_gpio->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	tc3589x_gpio->tc3589x = tc3589x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	tc3589x_gpio->chip = template_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	tc3589x_gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	tc3589x_gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	tc3589x_gpio->chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	girq = &tc3589x_gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	girq->chip = &tc3589x_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* Bring the GPIO module out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			       TC3589x_RSTCTRL_GPIRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 /* For tc35894, have to disable Direct KBD interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	  * else IRQST will always be 0x20, IRQN low level, can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	  * clear the irq status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	  * TODO: need more test on other tc3589x chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ret = devm_request_threaded_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					irq, NULL, tc3589x_gpio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 					IRQF_ONESHOT, "tc3589x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 					tc3589x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 				     tc3589x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	platform_set_drvdata(pdev, tc3589x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct platform_driver tc3589x_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.driver.name	= "tc3589x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.probe		= tc3589x_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int __init tc3589x_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return platform_driver_register(&tc3589x_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) subsys_initcall(tc3589x_gpio_init);