Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Abilis Systems MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) Abilis Systems 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *          Christian Ruppert <christian.ruppert@abilis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TB10X_GPIO_DIR_IN	(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TB10X_GPIO_DIR_OUT	(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OFFSET_TO_REG_DDR	(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OFFSET_TO_REG_DATA	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OFFSET_TO_REG_INT_EN	(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OFFSET_TO_REG_CHANGE	(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OFFSET_TO_REG_WRMASK	(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OFFSET_TO_REG_INT_TYPE	(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @base: register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @domain: IRQ domain of GPIO generated interrupts managed by this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @irq: Interrupt line of parent interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @gc: gpio_chip structure associated to this GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct tb10x_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return ioread32(gpio->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	iowrite32(val, gpio->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	r = tb10x_reg_read(gpio, offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	r = (r & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	tb10x_reg_write(gpio, offs, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return irq_create_mapping(tb10x_gpio->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		pr_err("Only (both) edge triggered interrupts supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	irqd_set_trigger_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct tb10x_gpio *tb10x_gpio = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	const unsigned long bits = r & m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	for_each_set_bit(i, &bits, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int tb10x_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct tb10x_gpio *tb10x_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u32 ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (tb10x_gpio == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	tb10x_gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (IS_ERR(tb10x_gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return PTR_ERR(tb10x_gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tb10x_gpio->gc.label =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!tb10x_gpio->gc.label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * Initialize generic GPIO with one single register for reading and setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * the lines, no special set or clear registers and a data direction register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * wher 1 means "output".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			 tb10x_gpio->base + OFFSET_TO_REG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			 tb10x_gpio->base + OFFSET_TO_REG_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		dev_err(dev, "unable to init generic GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tb10x_gpio->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	tb10x_gpio->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tb10x_gpio->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * ngpio is set by bgpio_init() but we override it, this .request()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * callback also overrides the one set up by generic GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	tb10x_gpio->gc.ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	tb10x_gpio->gc.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	tb10x_gpio->gc.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		dev_err(dev, "Could not add gpiochip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	platform_set_drvdata(pdev, tb10x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (of_find_property(np, "interrupt-controller", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		tb10x_gpio->gc.to_irq	= tb10x_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		tb10x_gpio->irq		= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				IRQF_TRIGGER_NONE | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				dev_name(dev), tb10x_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		tb10x_gpio->domain = irq_domain_add_linear(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 						tb10x_gpio->gc.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 						&irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (!tb10x_gpio->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		gc = tb10x_gpio->domain->gc->gc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		gc->reg_base                         = tb10x_gpio->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int tb10x_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (tb10x_gpio->gc.to_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		kfree(tb10x_gpio->domain->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		irq_domain_remove(tb10x_gpio->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct of_device_id tb10x_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ .compatible = "abilis,tb10x-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct platform_driver tb10x_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.probe		= tb10x_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.remove		= tb10x_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.name	= "tb10x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.of_match_table = tb10x_gpio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) module_platform_driver(tb10x_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DESCRIPTION("tb10x gpio.");