^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * peripheral controller used to drive external shift register cascades. At most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * to drive the 2 LSBs of the cascade automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* control register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XWAY_STP_CON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XWAY_STP_CON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* data register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XWAY_STP_CPU0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* data register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XWAY_STP_CPU1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* access register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XWAY_STP_AR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* software or hardware update select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XWAY_STP_CON_SWU BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* automatic update rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XWAY_STP_2HZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XWAY_STP_4HZ BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XWAY_STP_8HZ BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XWAY_STP_10HZ (BIT(24) | BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XWAY_STP_SPEED_MASK (BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XWAY_STP_FPIS_VALUE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XWAY_STP_FPIS_MASK (BIT(20) | BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* clock source for automatic update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XWAY_STP_UPD_FPI BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* let the adsl core drive the 2 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XWAY_STP_ADSL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XWAY_STP_ADSL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 2 groups of 3 bits can be driven by the phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XWAY_STP_PHY_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XWAY_STP_PHY1_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XWAY_STP_PHY2_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XWAY_STP_PHY3_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XWAY_STP_PHY4_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* STP has 3 groups of 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XWAY_STP_GROUP0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XWAY_STP_GROUP1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XWAY_STP_GROUP2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XWAY_STP_GROUP_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Edge configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XWAY_STP_FALLING BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XWAY_STP_EDGE_MASK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define xway_stp_r32(m, reg) __raw_readl(m + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define xway_stp_w32_mask(m, clear, set, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct xway_stp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 edge; /* rising or falling edge triggered shift register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 shadow; /* shadow the shift registers state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 groups; /* we can drive 1-3 groups of 8bit each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 dsl; /* the 2 LSBs can be driven by the dsl core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 phy1; /* 3 bits can be driven by phy1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 phy2; /* 3 bits can be driven by phy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 phy3; /* 3 bits can be driven by phy3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 phy4; /* 3 bits can be driven by phy4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 reserved; /* mask out the hw driven bits in gpio_request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * xway_stp_get() - gpio_chip->get - get gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @gc: Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @gpio: GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Gets the shadow value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct xway_stp *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * xway_stp_set() - gpio_chip->set - set gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @gc: Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @gpio: GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @val: Value to be written to specified signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Set the shadow value and call ltq_ebu_apply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct xway_stp *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) chip->shadow |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) chip->shadow &= ~BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!chip->reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @gc: Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @gpio: GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @val: Value to be written to specified signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Same as xway_stp_set, always returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) xway_stp_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * xway_stp_request() - gpio_chip->request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @gc: Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @gpio: GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * We mask out the HW driven pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct xway_stp *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @chip: Pointer to the xway_stp chip structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void xway_stp_hw_init(struct xway_stp *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* sane defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* apply edge trigger settings for the shift register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) chip->edge, XWAY_STP_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* apply led group settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) chip->groups, XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* tell the hardware which pins are controlled by the dsl modem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) xway_stp_w32_mask(chip->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) chip->dsl << XWAY_STP_ADSL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) XWAY_STP_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* tell the hardware which pins are controlled by the phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) xway_stp_w32_mask(chip->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) chip->phy1 << XWAY_STP_PHY1_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) XWAY_STP_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) xway_stp_w32_mask(chip->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) chip->phy2 << XWAY_STP_PHY2_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (of_machine_is_compatible("lantiq,grx390")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) || of_machine_is_compatible("lantiq,ar10")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) xway_stp_w32_mask(chip->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) XWAY_STP_PHY_MASK << XWAY_STP_PHY3_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) chip->phy3 << XWAY_STP_PHY3_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) xway_stp_w32_mask(chip->virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) XWAY_STP_PHY_MASK << XWAY_STP_PHY4_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) chip->phy4 << XWAY_STP_PHY4_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* mask out the hw driven bits in gpio_request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) | (chip->phy1 << 2) | chip->dsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * if we have pins that are driven by hw, we need to tell the stp what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * clock to use as a timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (chip->reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) XWAY_STP_UPD_FPI, XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) XWAY_STP_10HZ, XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) XWAY_STP_FPIS_VALUE, XWAY_STP_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int xway_stp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 shadow, groups, dsl, phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct xway_stp *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) chip->virt = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(chip->virt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return PTR_ERR(chip->virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) chip->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) chip->gc.label = "stp-xway";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) chip->gc.direction_output = xway_stp_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) chip->gc.get = xway_stp_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) chip->gc.set = xway_stp_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chip->gc.request = xway_stp_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) chip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) chip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* store the shadow value if one was passed by the devicetree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) chip->shadow = shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* find out which gpio groups should be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) chip->groups = groups & XWAY_STP_GROUP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) chip->groups = XWAY_STP_GROUP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) chip->gc.ngpio = fls(chip->groups) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* find out which gpios are controlled by the dsl core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chip->dsl = dsl & XWAY_STP_ADSL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* find out which gpios are controlled by the phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (of_machine_is_compatible("lantiq,ar9") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) of_machine_is_compatible("lantiq,gr9") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) of_machine_is_compatible("lantiq,vr9") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) of_machine_is_compatible("lantiq,ar10") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) chip->phy1 = phy & XWAY_STP_PHY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) chip->phy2 = phy & XWAY_STP_PHY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (of_machine_is_compatible("lantiq,ar10") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) chip->phy3 = phy & XWAY_STP_PHY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) chip->phy4 = phy & XWAY_STP_PHY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* check which edge trigger we should use, default to a falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) chip->edge = XWAY_STP_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(&pdev->dev, "Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) xway_stp_hw_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_info(&pdev->dev, "Init done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct of_device_id xway_stp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .compatible = "lantiq,gpio-stp-xway" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_DEVICE_TABLE(of, xway_stp_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct platform_driver xway_stp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .probe = xway_stp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "gpio-stp-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .of_match_table = xway_stp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __init xway_stp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return platform_driver_register(&xway_stp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) subsys_initcall(xway_stp_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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