^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/stmpe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * These registers are modified under the irq bus lock and cached to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * unnecessary writes in bus_sync_unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum { REG_RE, REG_FE, REG_IE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum { LSB, CSB, MSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CACHE_NR_REGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* No variant has more than 24 GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CACHE_NR_BANKS (24 / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct stmpe_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct stmpe *stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 norequest_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Caches of interrupt control registers for bus_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ret = stmpe_reg_read(stmpe, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 reg = stmpe->regs[which + (offset / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Some variants have single register for gpio set/clear functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * For them we need to write 0 to clear and 1 to set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) stmpe_reg_write(stmpe, reg, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int stmpe_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = stmpe_reg_read(stmpe, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int stmpe_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) stmpe_gpio_set(chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return stmpe_set_bits(stmpe, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int stmpe_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return stmpe_set_bits(stmpe, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (stmpe_gpio->norequest_mask & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct gpio_chip template_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .label = "stmpe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .get_direction = stmpe_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .direction_input = stmpe_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .get = stmpe_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .direction_output = stmpe_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .set = stmpe_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .request = stmpe_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* STMPE801 and STMPE 1600 don't have RE and FE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (stmpe_gpio->stmpe->partnum == STMPE801 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) stmpe_gpio->stmpe->partnum == STMPE1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) stmpe_gpio->regs[REG_RE][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) stmpe_gpio->regs[REG_FE][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void stmpe_gpio_irq_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mutex_lock(&stmpe_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * STMPE1600: to be able to get IRQ from pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * a read must be done on GPMR register, or a write in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * GPSR or GPCR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (stmpe->partnum == STMPE1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < CACHE_NR_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* STMPE801 and STMPE1600 don't have RE and FE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if ((stmpe->partnum == STMPE801 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) stmpe->partnum == STMPE1600) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (i != REG_IE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (j = 0; j < num_banks; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 old = stmpe_gpio->oldregs[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 new = stmpe_gpio->regs[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (new == old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) stmpe_gpio->oldregs[i][j] = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mutex_unlock(&stmpe_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void stmpe_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void stmpe_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int regoffset = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) stmpe_gpio->regs[REG_IE][regoffset] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void stmpe_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned offset, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const char *label = gpiochip_is_requested(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool val = !!stmpe_gpio_get(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 bank = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = stmpe_reg_read(stmpe, dir_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dir = !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) gpio, label ?: "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val ? "hi" : "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 edge_det_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 rise_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 fall_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 irqen_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const char * const edge_det_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "edge-inactive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "edge-asserted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "not-supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char * const rise_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "no-rising-edge-detection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "rising-edge-detection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "not-supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const fall_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "no-falling-edge-detection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "falling-edge-detection",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "not-supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define NOT_SUPPORTED_IDX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 edge_det = NOT_SUPPORTED_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 rise = NOT_SUPPORTED_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 fall = NOT_SUPPORTED_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool irqen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (stmpe->partnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case STMPE610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case STMPE811:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case STMPE1601:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case STMPE2401:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case STMPE2403:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = stmpe_reg_read(stmpe, edge_det_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) edge_det = !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case STMPE1801:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = stmpe_reg_read(stmpe, rise_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rise = !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = stmpe_reg_read(stmpe, fall_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fall = !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case STMPE801:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case STMPE1600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = stmpe_reg_read(stmpe, irqen_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) irqen = !!(ret & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) gpio, label ?: "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) edge_det_values[edge_det],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) irqen ? "IRQ-enabled" : "IRQ-disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rise_values[rise],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) fall_values[fall]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned gpio = gc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) for (i = 0; i < gc->ngpio; i++, gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) stmpe_dbg_show_one(s, gc, i, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) seq_putc(s, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct irq_chip stmpe_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "stmpe-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .irq_bus_lock = stmpe_gpio_irq_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .irq_mask = stmpe_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .irq_unmask = stmpe_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .irq_set_type = stmpe_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MAX_GPIOS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct stmpe_gpio *stmpe_gpio = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct stmpe *stmpe = stmpe_gpio->stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 statmsbreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * the stmpe_block_read() call below, imposes to set statmsbreg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * with the register located at the lowest address. As STMPE1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * variant is the only one which respect registers address's order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * (LSB regs located at lowest address than MSB ones) whereas all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * the others have a registers layout with MSB located before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * LSB regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (stmpe->partnum == STMPE1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (i = 0; i < num_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) num_banks - i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int stat = status[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) stat &= enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int bit = __ffs(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int line = bank * 8 + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) handle_nested_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) stat &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * interrupt status register write has no effect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * 801/1801/1600, bits are cleared when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Edge detect register is not present on 801/1600/1801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) stmpe->partnum != STMPE1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) stmpe_reg_write(stmpe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long *valid_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!stmpe_gpio->norequest_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Forbid unused lines to be mapped as IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < sizeof(u32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (stmpe_gpio->norequest_mask & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clear_bit(i, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int stmpe_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct stmpe_gpio *stmpe_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (stmpe->num_gpios > MAX_GPIOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!stmpe_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mutex_init(&stmpe_gpio->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) stmpe_gpio->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) stmpe_gpio->stmpe = stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) stmpe_gpio->chip = template_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) stmpe_gpio->chip.ngpio = stmpe->num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) stmpe_gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) stmpe_gpio->chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) stmpe_gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * REVISIT: this makes sure the valid mask gets allocated and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * filled in when adding the gpio_chip, but the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * gpio_irqchip is still filled in using the old method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * in gpiochip_irqchip_add_nested() so clean this up once we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * get the gpio_irqchip to initialize while adding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * gpio_chip also for threaded irqchips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (IS_ENABLED(CONFIG_DEBUG_FS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) of_property_read_u32(np, "st,norequest-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &stmpe_gpio->norequest_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "device configured in no-irq mode: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "irqs are not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) stmpe_gpio_irq, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "stmpe-gpio", stmpe_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) girq = &stmpe_gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) girq->chip = &stmpe_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) platform_set_drvdata(pdev, stmpe_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gpiochip_remove(&stmpe_gpio->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) kfree(stmpe_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct platform_driver stmpe_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "stmpe-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .probe = stmpe_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int __init stmpe_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return platform_driver_register(&stmpe_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) subsys_initcall(stmpe_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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