Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * STMicroelectronics ConneXt (STA2X11) GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2012 ST Microelectronics (Alessandro Rubini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mfd/sta2x11-mfd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct gsta_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32 dat;		/* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 dats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 datc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32 pdis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32 dir;		/* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 dirs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 dirc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 unused_1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 afsela;		/* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 unused_24[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 rimsc;		/* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 fimsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 is;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct gsta_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	spinlock_t			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct device			*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void __iomem			*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct gsta_regs __iomem	*regs[GSTA_NR_BLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct gpio_chip		gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int				irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* FIXME: save the whole config here (AF, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned			irq_type[GSTA_NR_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * gpio methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct gsta_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		writel(bit, &regs->dats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		writel(bit, &regs->datc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct gsta_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return !!(readl(&regs->dat) & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				      int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct gsta_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writel(bit, &regs->dirs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Data register after direction, otherwise pullup/down is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		writel(bit, &regs->dats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		writel(bit, &regs->datc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct gsta_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	writel(bit, &regs->dirc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct gsta_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return chip->irq_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct gpio_chip *gpio = &chip->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * from the end. However, for compatibility, we need the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * ConneXt device to start from gpio 0: it's the main chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * on most boards so documents and drivers assume gpio0..gpio127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	static int gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	gpio->label = dev_name(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	gpio->direction_input = gsta_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	gpio->get = gsta_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	gpio->direction_output = gsta_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	gpio->set = gsta_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	gpio->dbg_show = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	gpio->base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	gpio->ngpio = GSTA_NR_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	gpio->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	gpio->to_irq = gsta_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * After the first device, turn to dynamic gpio numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (!gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		gpio_base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * Special method: alternate functions and pullup/pulldown. This is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * invoked on startup to configure gpio's according to platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * FIXME : this functionality shall be managed (and exported to other drivers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * via the pin control subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (cfg == PINMUX_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Alternate function or not? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	val = readl(&regs->afsela);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (cfg == PINMUX_TYPE_FUNCTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		val |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		val &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	writel(val | bit, &regs->afsela);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (cfg == PINMUX_TYPE_FUNCTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* not alternate function: set details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	switch (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	case PINMUX_TYPE_OUTPUT_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		writel(bit, &regs->dirs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		writel(bit, &regs->datc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case PINMUX_TYPE_OUTPUT_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		writel(bit, &regs->dirs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		writel(bit, &regs->dats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case PINMUX_TYPE_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		writel(bit, &regs->dirc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		val = readl(&regs->pdis) | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		writel(val, &regs->pdis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case PINMUX_TYPE_INPUT_PULLUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		writel(bit, &regs->dirc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		val = readl(&regs->pdis) & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		writel(val, &regs->pdis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		writel(bit, &regs->dats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case PINMUX_TYPE_INPUT_PULLDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		writel(bit, &regs->dirc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		val = readl(&regs->pdis) & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		writel(val, &regs->pdis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		writel(bit, &regs->datc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		       __func__, chip, nr, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * Irq methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void gsta_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct gsta_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int nr = data->irq - chip->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		val = readl(&regs->rimsc) & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		writel(val, &regs->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		val = readl(&regs->fimsc) & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		writel(val, &regs->fimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void gsta_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct gsta_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int nr = data->irq - chip->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	type = chip->irq_type[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	val = readl(&regs->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		writel(val | bit, &regs->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		writel(val & ~bit, &regs->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	val = readl(&regs->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		writel(val | bit, &regs->fimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		writel(val & ~bit, &regs->fimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int gsta_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct gsta_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int nr = d->irq - chip->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* We only support edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		pr_debug("%s: unsupported type 0x%x\n", __func__, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	chip->irq_type[nr] = type; /* used for enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	gsta_irq_enable(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct gsta_gpio *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct gsta_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	u32 is;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int i, nr, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		regs = chip->regs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		while ((is = readl(&regs->is))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			nr = __ffs(is);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			irq = base + nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			writel(1 << nr, &regs->ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					 chip->irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					 chip->reg_base, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	gc->private = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ct->chip.irq_set_type = gsta_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	ct->chip.irq_disable = gsta_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	ct->chip.irq_enable = gsta_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	rv = devm_irq_setup_generic_chip(chip->dev, gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 					 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 					 0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* Set up all all 128 interrupts: code from setup_generic_chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		for (j = 0; j < GSTA_NR_GPIO; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			i = chip->irq_base + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			irq_set_chip_and_handler(i, &ct->chip, ct->handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			irq_set_chip_data(i, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		gc->irq_cnt = i - gc->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* The platform device used here is instantiated by the MFD device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int gsta_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct sta2x11_gpio_pdata *gpio_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct gsta_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	gpio_pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (gpio_pdata == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		dev_err(&dev->dev, "no gpio config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pr_debug("gpio config: %p\n", gpio_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	chip->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	chip->reg_base = devm_platform_ioremap_resource(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (IS_ERR(chip->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return PTR_ERR(chip->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		chip->regs[i] = chip->reg_base + i * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		/* disable all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		writel(0, &chip->regs[i]->rimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		writel(0, &chip->regs[i]->fimsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		writel(~0, &chip->regs[i]->ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	gsta_gpio_setup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (gpio_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		for (i = 0; i < GSTA_NR_GPIO; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* 384 was used in previous code: be compatible for other drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	err = devm_irq_alloc_descs(&dev->dev, -1, 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 				   GSTA_NR_GPIO, NUMA_NO_NODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			 -err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	chip->irq_base = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	err = gsta_alloc_irq_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	err = devm_request_irq(&dev->dev, pdev->irq, gsta_gpio_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			       IRQF_SHARED, KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			-err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			-err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	platform_set_drvdata(dev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct platform_driver sta2x11_gpio_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		.name	= "sta2x11-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.probe = gsta_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) builtin_platform_driver(sta2x11_gpio_platform_driver);