Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2018 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* GPIO registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SPRD_GPIO_DATA		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SPRD_GPIO_DMSK		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SPRD_GPIO_DIR		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SPRD_GPIO_IS		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SPRD_GPIO_IBE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SPRD_GPIO_IEV		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SPRD_GPIO_IE		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SPRD_GPIO_RIS		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SPRD_GPIO_MIS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SPRD_GPIO_IC		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SPRD_GPIO_INEN		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SPRD_GPIO_BANK_NR	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPRD_GPIO_NR		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SPRD_GPIO_BANK_SIZE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SPRD_GPIO_BANK_MASK	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SPRD_GPIO_BIT(x)	((x) & (SPRD_GPIO_BANK_NR - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct sprd_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 						unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			     u16 reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 						 offset / SPRD_GPIO_BANK_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	spin_lock_irqsave(&sprd_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	tmp = readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		tmp |= BIT(SPRD_GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		tmp &= ~BIT(SPRD_GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel_relaxed(tmp, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	spin_unlock_irqrestore(&sprd_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						 offset / SPRD_GPIO_BANK_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int sprd_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				     unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int sprd_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				      unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			  int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void sprd_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void sprd_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void sprd_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int sprd_gpio_irq_set_type(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				  unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void sprd_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct irq_chip *ic = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 bank, n, girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	chained_irq_enter(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			SPRD_GPIO_BANK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			girq = irq_find_mapping(chip->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 						bank * SPRD_GPIO_BANK_NR + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			generic_handle_irq(girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	chained_irq_exit(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct irq_chip sprd_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.name = "sprd-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.irq_ack = sprd_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.irq_mask = sprd_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.irq_unmask = sprd_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.irq_set_type = sprd_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int sprd_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct sprd_gpio *sprd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!sprd_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	sprd_gpio->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (sprd_gpio->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return sprd_gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (IS_ERR(sprd_gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return PTR_ERR(sprd_gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	spin_lock_init(&sprd_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	sprd_gpio->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	sprd_gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	sprd_gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	sprd_gpio->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	sprd_gpio->chip.request = sprd_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	sprd_gpio->chip.free = sprd_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	sprd_gpio->chip.get = sprd_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	sprd_gpio->chip.set = sprd_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	irq = &sprd_gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	irq->chip = &sprd_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	irq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	irq->parent_handler = sprd_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	irq->parent_handler_data = sprd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	irq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	irq->parents = &sprd_gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	platform_set_drvdata(pdev, sprd_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct of_device_id sprd_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{ .compatible = "sprd,sc9860-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	{ /* end of list */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct platform_driver sprd_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.probe = sprd_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.name = "sprd-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.of_match_table	= sprd_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DESCRIPTION("Spreadtrum GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_LICENSE("GPL v2");