^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SPEAr platform SPI chipselect abstraction over gpiolib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* maximum chipselects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NUM_OF_GPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * through system registers. This register lies outside spi (pl022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * address space into system registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * It provides control for spi chip select lines so that any chipselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (out of 4 possible chipselects in pl022) can be made low to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the particular slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct spear_spics - represents spi chip select control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @base: base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @perip_cfg: configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @sw_enable_bit: bit to enable s/w control over chipselects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @cs_value_bit: bit to program high or low chipselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @cs_enable_mask: mask to select bits required to select chipselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @cs_enable_shift: bit pos of cs_enable_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @use_count: use count of a spi controller cs lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @last_off: stores last offset caller of set_value()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @chip: gpio_chip abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct spear_spics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 perip_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 sw_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 cs_value_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 cs_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 cs_enable_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long use_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int last_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* gpio framework specific routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int spics_get_value(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct spear_spics *spics = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* select chip select from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tmp = readl_relaxed(spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (spics->last_off != offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spics->last_off = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tmp |= offset << spics->cs_enable_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* toggle chip select line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tmp &= ~(0x1 << spics->cs_value_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tmp |= value << spics->cs_value_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(tmp, spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spics_set_value(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int spics_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct spear_spics *spics = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!spics->use_count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmp = readl_relaxed(spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tmp |= 0x1 << spics->sw_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp |= 0x1 << spics->cs_value_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(tmp, spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void spics_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct spear_spics *spics = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!--spics->use_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tmp = readl_relaxed(spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp &= ~(0x1 << spics->sw_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel_relaxed(tmp, spics->base + spics->perip_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int spics_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct spear_spics *spics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!spics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spics->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(spics->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PTR_ERR(spics->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (of_property_read_u32(np, "st-spics,peripcfg-reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &spics->perip_cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto err_dt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (of_property_read_u32(np, "st-spics,sw-enable-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &spics->sw_enable_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto err_dt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (of_property_read_u32(np, "st-spics,cs-value-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &spics->cs_value_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err_dt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (of_property_read_u32(np, "st-spics,cs-enable-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &spics->cs_enable_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto err_dt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (of_property_read_u32(np, "st-spics,cs-enable-shift",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &spics->cs_enable_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto err_dt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) platform_set_drvdata(pdev, spics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spics->chip.ngpio = NUM_OF_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spics->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spics->chip.request = spics_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spics->chip.free = spics_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spics->chip.direction_input = spics_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spics->chip.direction_output = spics_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spics->chip.get = spics_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spics->chip.set = spics_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spics->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spics->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spics->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spics->last_off = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(&pdev->dev, "unable to add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_info(&pdev->dev, "spear spics registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) err_dt_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(&pdev->dev, "DT probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct of_device_id spics_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .compatible = "st,spear-spics-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct platform_driver spics_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .probe = spics_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "spear-spics-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .of_match_table = spics_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int __init spics_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return platform_driver_register(&spics_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) subsys_initcall(spics_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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