Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  GPIO interface for Intel Sodaville SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2010, 2011 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Author: Hans J. Koch <hjk@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DRV_NAME		"sdv_gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SDV_NUM_PUB_GPIOS	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCI_DEVICE_ID_SDV_GPIO	0x2e67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GPIO_BAR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GPOUTR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GPOER		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GPINR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GPSTR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GPIT1R0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPIO_INT	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GPIT1R1		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPMUXCTL	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct sdv_gpio_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	void __iomem *gpio_pub_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct irq_domain *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct sdv_gpio_chip_data *sd = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *type_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (d->hwirq < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		type_reg = sd->gpio_pub_base + GPIT1R0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		type_reg = sd->gpio_pub_base + GPIT1R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	reg = readl(type_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		reg &= ~BIT(4 * (d->hwirq % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		reg |= BIT(4 * (d->hwirq % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writel(reg, type_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct sdv_gpio_chip_data *sd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (!irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	for_each_set_bit(irq_bit, &irq_stat, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int sdv_xlate(struct irq_domain *h, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		u32 *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 line, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (node != irq_domain_get_of_node(h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (intsize < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	line = *intspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	*out_hwirq = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	intspec++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	type = *intspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		*out_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct irq_domain_ops irq_domain_sdv_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.xlate = sdv_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 					    SDV_NUM_PUB_GPIOS, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (sd->irq_base < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return sd->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* mask + ACK all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel(0, sd->gpio_pub_base + GPIO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = devm_request_irq(&pdev->dev, pdev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			       sdv_gpio_pub_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			       "sdv_gpio", sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * This gpio irq controller latches level irqs. Testing shows that if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * we unmask & ACK the IRQ before the source of the interrupt is gone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * then the interrupt is active again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					     sd->irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 					     sd->gpio_pub_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					     handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (!sd->gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	sd->gc->private = sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ct = sd->gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ct->regs.eoi = GPSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ct->regs.mask = GPIO_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ct->chip.irq_eoi = irq_gc_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ct->chip.irq_set_type = sdv_gpio_pub_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			IRQ_LEVEL | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				sd->irq_base, 0, &irq_domain_sdv_ops, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!sd->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int sdv_gpio_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct sdv_gpio_chip_data *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 mux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dev_err(&pdev->dev, "can't enable device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = bgpio_init(&sd->chip, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			NULL, sd->gpio_pub_base + GPOER, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_err(&pdev->dev, "gpiochip_add() failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = sdv_register_irqsupport(sd, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	pci_set_drvdata(pdev, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct pci_device_id sdv_gpio_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct pci_driver sdv_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.id_table = sdv_gpio_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.probe = sdv_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) builtin_pci_driver(sdv_gpio_driver);