^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/siox.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct gpio_siox_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct gpio_chip gchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct irq_chip ichip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u8 setdata[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 getdata[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) raw_spinlock_t irqlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 irq_type[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Note that this callback only sets the value that is clocked out in the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int gpio_siox_set_data(struct siox_device *sdevice, u8 status, u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) buf[0] = ddata->setdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int gpio_siox_get_data(struct siox_device *sdevice, const u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) size_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) raw_spin_lock_irq(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) for (offset = 0; offset < 12; ++offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int bitpos = 11 - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int gpiolevel = buf[bitpos / 8] & (1 << bitpos % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int prev_level =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 irq_type = ddata->irq_type[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (gpiolevel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if ((irq_type & IRQ_TYPE_LEVEL_HIGH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ((irq_type & IRQ_TYPE_EDGE_RISING) && !prev_level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ddata->irq_status |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((irq_type & IRQ_TYPE_LEVEL_LOW) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ((irq_type & IRQ_TYPE_EDGE_FALLING) && prev_level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ddata->irq_status |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) trigger = ddata->irq_status & ddata->irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) raw_spin_unlock_irq(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ddata->getdata[0] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ddata->getdata[1] = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ddata->getdata[2] = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (offset = 0; offset < 12; ++offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (trigger & (1 << offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct irq_domain *irqdomain = ddata->gchip.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int irq = irq_find_mapping(irqdomain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Conceptually handle_nested_irq should call the flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * handler of the irq chip. But it doesn't, so we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * to clean the irq_status here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) raw_spin_lock_irq(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ddata->irq_status &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) raw_spin_unlock_irq(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) handle_nested_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void gpio_siox_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct irq_chip *ic = irq_data_get_irq_chip(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) container_of(ic, struct gpio_siox_ddata, ichip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) raw_spin_lock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ddata->irq_status &= ~(1 << d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) raw_spin_unlock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void gpio_siox_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct irq_chip *ic = irq_data_get_irq_chip(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) container_of(ic, struct gpio_siox_ddata, ichip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) raw_spin_lock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ddata->irq_enable &= ~(1 << d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raw_spin_unlock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void gpio_siox_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct irq_chip *ic = irq_data_get_irq_chip(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) container_of(ic, struct gpio_siox_ddata, ichip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) raw_spin_lock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ddata->irq_enable |= 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) raw_spin_unlock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int gpio_siox_irq_set_type(struct irq_data *d, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct irq_chip *ic = irq_data_get_irq_chip(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) container_of(ic, struct gpio_siox_ddata, ichip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) raw_spin_lock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ddata->irq_type[d->hwirq] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_unlock(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int gpio_siox_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) container_of(chip, struct gpio_siox_ddata, gchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (offset >= 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int bitpos = 19 - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = ddata->setdata[0] & (1 << bitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int bitpos = 11 - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void gpio_siox_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct gpio_siox_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) container_of(chip, struct gpio_siox_ddata, gchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 mask = 1 << (19 - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ddata->setdata[0] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ddata->setdata[0] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int gpio_siox_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (offset >= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int gpio_siox_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (offset < 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) gpio_siox_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (offset < 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int gpio_siox_probe(struct siox_device *sdevice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct gpio_siox_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct device *dev = &sdevice->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_set_drvdata(dev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mutex_init(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) raw_spin_lock_init(&ddata->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ddata->gchip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ddata->gchip.can_sleep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ddata->gchip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ddata->gchip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ddata->gchip.get = gpio_siox_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ddata->gchip.set = gpio_siox_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ddata->gchip.direction_input = gpio_siox_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ddata->gchip.direction_output = gpio_siox_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ddata->gchip.get_direction = gpio_siox_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ddata->gchip.ngpio = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ddata->ichip.name = "siox-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ddata->ichip.irq_ack = gpio_siox_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ddata->ichip.irq_mask = gpio_siox_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ddata->ichip.irq_unmask = gpio_siox_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ddata->ichip.irq_set_type = gpio_siox_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) girq = &ddata->gchip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) girq->chip = &ddata->ichip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = devm_gpiochip_add_data(dev, &ddata->gchip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(dev, "Failed to register gpio chip (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct siox_driver gpio_siox_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe = gpio_siox_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .set_data = gpio_siox_set_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .get_data = gpio_siox_get_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "gpio-siox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) module_siox_driver(gpio_siox_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DESCRIPTION("SIOX gpio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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