^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIFIVE_GPIO_INPUT_VAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIFIVE_GPIO_INPUT_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIFIVE_GPIO_OUTPUT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIFIVE_GPIO_OUTPUT_VAL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIFIVE_GPIO_RISE_IE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIFIVE_GPIO_RISE_IP 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIFIVE_GPIO_FALL_IE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIFIVE_GPIO_FALL_IP 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIFIVE_GPIO_HIGH_IE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIFIVE_GPIO_HIGH_IP 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIFIVE_GPIO_LOW_IE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIFIVE_GPIO_LOW_IP 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIFIVE_GPIO_OUTPUT_XOR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIFIVE_GPIO_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIFIVE_GPIO_IRQ_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sifive_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long irq_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int trigger[SIFIVE_GPIO_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int irq_parent[SIFIVE_GPIO_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct sifive_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (offset < 0 || offset >= gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) chip->trigger[offset] = trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sifive_gpio_set_ie(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void sifive_gpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sifive_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) irq_chip_enable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Switch to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) gc->direction_input(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Clear any sticky pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) assign_bit(offset, &chip->irq_state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sifive_gpio_set_ie(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void sifive_gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sifive_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) assign_bit(offset, &chip->irq_state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) sifive_gpio_set_ie(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_chip_disable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void sifive_gpio_irq_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct sifive_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct irq_chip sifive_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "sifive-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .irq_set_type = sifive_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .irq_enable = sifive_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .irq_disable = sifive_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .irq_eoi = sifive_gpio_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int child_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int *parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *parent_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *parent = child + SIFIVE_GPIO_IRQ_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regmap_config sifive_gpio_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .disable_locking = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int sifive_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct device_node *irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct irq_domain *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sifive_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret, ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (IS_ERR(chip->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(dev, "failed to allocate device memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chip->regs = devm_regmap_init_mmio(dev, chip->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &sifive_gpio_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(chip->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return PTR_ERR(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ngpio = of_irq_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ngpio > SIFIVE_GPIO_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SIFIVE_GPIO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irq_parent = of_irq_find_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!irq_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(dev, "no IRQ parent node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) parent = irq_find_host(irq_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "no IRQ parent domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = bgpio_init(&chip->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) chip->base + SIFIVE_GPIO_INPUT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) chip->base + SIFIVE_GPIO_OUTPUT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) chip->base + SIFIVE_GPIO_OUTPUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) chip->base + SIFIVE_GPIO_INPUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BGPIOF_READ_OUTPUT_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(dev, "unable to init generic GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Disable all GPIO interrupts before enabling parent interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) chip->irq_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) chip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chip->gc.ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) chip->gc.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) chip->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) chip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) girq = &chip->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) girq->chip = &sifive_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) girq->fwnode = of_node_to_fwnode(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) girq->parent_domain = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return gpiochip_add_data(&chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct of_device_id sifive_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .compatible = "sifive,gpio0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "sifive,fu540-c000-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver sifive_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .probe = sifive_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "sifive_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .of_match_table = of_match_ptr(sifive_gpio_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) builtin_platform_driver(sifive_gpio_driver)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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