^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO interface for Intel Poulsbo SCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 CompuLab Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Denis Turischev <denis@compulab.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GEN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GIO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GLV 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct sch_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned short iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned short resume_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (gpio >= sch->resume_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) gpio -= sch->resume_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) base += 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return base + reg + gpio / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (gpio >= sch->resume_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) gpio -= sch->resume_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return gpio % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned short offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) offset = sch_gpio_offset(sch, gpio, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bit = sch_gpio_bit(sch, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned short offset, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) offset = sch_gpio_offset(sch, gpio, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bit = sch_gpio_bit(sch, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg_val = inb(sch->iobase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) outb(reg_val | BIT(bit), sch->iobase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) outb((reg_val & ~BIT(bit)), sch->iobase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct sch_gpio *sch = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spin_lock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) sch_gpio_reg_set(sch, gpio_num, GIO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spin_unlock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sch_gpio *sch = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return sch_gpio_reg_get(sch, gpio_num, GLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sch_gpio *sch = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spin_lock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sch_gpio_reg_set(sch, gpio_num, GLV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_unlock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct sch_gpio *sch = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_lock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sch_gpio_reg_set(sch, gpio_num, GIO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_unlock(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * according to the datasheet, writing to the level register has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * effect when GPIO is programmed as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Actually the the level register is read-only when configured as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Thus presetting the output level before switching to output is _NOT_ possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Hence we set the level after configuring the GPIO as output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * But we cannot prevent a short low pulse if direction is set to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * and an external pull-up is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sch_gpio_set(gc, gpio_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct sch_gpio *sch = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (sch_gpio_reg_get(sch, gpio_num, GIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct gpio_chip sch_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .label = "sch_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .direction_input = sch_gpio_direction_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .get = sch_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .direction_output = sch_gpio_direction_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .set = sch_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .get_direction = sch_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int sch_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sch_gpio *sch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!sch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pdev->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spin_lock_init(&sch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sch->iobase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sch->chip = sch_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sch->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) sch->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (pdev->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case PCI_DEVICE_ID_INTEL_SCH_LPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sch->resume_base = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sch->chip.ngpio = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * GPIO[6:0] enabled by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * GPIO7 is configured by the CMC as SLPIOVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Enable GPIO[9:8] core powered gpios explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sch_gpio_reg_set(sch, 8, GEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sch_gpio_reg_set(sch, 9, GEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * SUS_GPIO[2:0] enabled by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Enable SUS_GPIO3 resume powered gpio explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sch_gpio_reg_set(sch, 13, GEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case PCI_DEVICE_ID_INTEL_ITC_LPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sch->resume_base = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sch->chip.ngpio = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sch->resume_base = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sch->chip.ngpio = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sch->resume_base = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sch->chip.ngpio = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) platform_set_drvdata(pdev, sch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct platform_driver sch_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "sch_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .probe = sch_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) module_platform_driver(sch_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_ALIAS("platform:sch_gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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