^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SAMA5D2 PIOBU GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andrei Stefanescu <andrei.stefanescu@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIOBU_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIOBU_REG_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * backup mode protection register for tamper detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * normal mode protection register for tamper detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * wakeup signal generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIOBU_BMPR 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PIOBU_NMPR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PIOBU_WKPR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIOBU_BASE 0x18 /* PIOBU offset from SECUMOD base register address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PIOBU_DET_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* In the datasheet this bit is called OUTPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PIOBU_DIRECTION BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PIOBU_OUT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIOBU_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIOBU_SOD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIOBU_PDS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIOBU_HIGH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIOBU_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct sama5d2_piobu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * sama5d2_piobu_setup_pin() - prepares a pin for set_direction call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Do not consider pin for tamper detection (normal and backup modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Do not consider pin as tamper wakeup interrupt source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int sama5d2_piobu_setup_pin(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int mask = BIT(PIOBU_DET_OFFSET + pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = regmap_update_bits(piobu->regmap, PIOBU_BMPR, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = regmap_update_bits(piobu->regmap, PIOBU_NMPR, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return regmap_update_bits(piobu->regmap, PIOBU_WKPR, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * sama5d2_piobu_write_value() - writes value & mask at the pin's PIOBU register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int sama5d2_piobu_write_value(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int mask, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = PIOBU_BASE + pin * PIOBU_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return regmap_update_bits(piobu->regmap, reg, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * sama5d2_piobu_read_value() - read the value with masking from the pin's PIOBU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int sama5d2_piobu_read_value(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg = PIOBU_BASE + pin * PIOBU_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = regmap_read(piobu->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * sama5d2_piobu_get_direction() - gpiochip get_direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret = sama5d2_piobu_read_value(chip, pin, PIOBU_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return (ret == PIOBU_IN) ? GPIO_LINE_DIRECTION_IN :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * sama5d2_piobu_direction_input() - gpiochip direction_input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, PIOBU_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * sama5d2_piobu_direction_output() - gpiochip direction_output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int sama5d2_piobu_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int pin, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int val = PIOBU_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val |= PIOBU_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION | PIOBU_SOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * sama5d2_piobu_get() - gpiochip get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int sama5d2_piobu_get(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* if pin is input, read value from PDS else read from SOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret = sama5d2_piobu_get_direction(chip, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret == GPIO_LINE_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = sama5d2_piobu_read_value(chip, pin, PIOBU_PDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else if (ret == GPIO_LINE_DIRECTION_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = sama5d2_piobu_read_value(chip, pin, PIOBU_SOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return !!ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * sama5d2_piobu_set() - gpiochip set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void sama5d2_piobu_set(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) value = PIOBU_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) value = PIOBU_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sama5d2_piobu_write_value(chip, pin, PIOBU_SOD, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int sama5d2_piobu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct sama5d2_piobu *piobu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) piobu = devm_kzalloc(&pdev->dev, sizeof(*piobu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!piobu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) platform_set_drvdata(pdev, piobu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) piobu->chip.label = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) piobu->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) piobu->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) piobu->chip.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) piobu->chip.get_direction = sama5d2_piobu_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) piobu->chip.direction_input = sama5d2_piobu_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) piobu->chip.direction_output = sama5d2_piobu_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) piobu->chip.get = sama5d2_piobu_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) piobu->chip.set = sama5d2_piobu_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) piobu->chip.base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) piobu->chip.ngpio = PIOBU_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) piobu->chip.can_sleep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) piobu->regmap = syscon_node_to_regmap(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (IS_ERR(piobu->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(&pdev->dev, "Failed to get syscon regmap %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PTR_ERR(piobu->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return PTR_ERR(piobu->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = devm_gpiochip_add_data(&pdev->dev, &piobu->chip, piobu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(&pdev->dev, "Failed to add gpiochip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (i = 0; i < PIOBU_NUM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = sama5d2_piobu_setup_pin(&piobu->chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(&pdev->dev, "Failed to setup pin: %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id sama5d2_piobu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .compatible = "atmel,sama5d2-secumod" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, sama5d2_piobu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct platform_driver sama5d2_piobu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "sama5d2-piobu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .of_match_table = of_match_ptr(sama5d2_piobu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .probe = sama5d2_piobu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) module_platform_driver(sama5d2_piobu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("SAMA5D2 PIOBU controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_AUTHOR("Andrei Stefanescu <andrei.stefanescu@microchip.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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