Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-sa1100/gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Generic SA-1100 GPIO handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <soc/sa1100/pwer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct sa1100_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	int irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u32 irqrising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32 irqfalling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 irqwake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	R_GPLR = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	R_GPDR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	R_GPSR = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	R_GPCR = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	R_GRER = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	R_GFER = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	R_GEDR = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	R_GAFR = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int reg = value ? R_GPSR : R_GPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (readl_relaxed(gpdr) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	sa1100_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return sa1100_gpio_chip(chip)->irqbase + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static struct sa1100_gpio_chip sa1100_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.label			= "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.get_direction		= sa1100_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.direction_input	= sa1100_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.direction_output	= sa1100_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.set			= sa1100_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.get			= sa1100_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.to_irq			= sa1100_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.base			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.ngpio			= GPIO_MAX + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.membase = (void *)&GPLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.irqbase = IRQ_GPIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * SA1100 GPIO edge detection for IRQs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * Use this instead of directly setting GRER/GFER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	void *base = sgc->membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 grer, gfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	grer = sgc->irqrising & sgc->irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	gfer = sgc->irqfalling & sgc->irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	writel_relaxed(grer, base + R_GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	writel_relaxed(gfer, base + R_GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (type == IRQ_TYPE_PROBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if ((sgc->irqrising | sgc->irqfalling) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		sgc->irqrising |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		sgc->irqrising &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		sgc->irqfalling |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		sgc->irqfalling &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	sa1100_update_edge_regs(sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * GPIO IRQs must be acknowledged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void sa1100_gpio_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void sa1100_gpio_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned int mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	sgc->irqmask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	sa1100_update_edge_regs(sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void sa1100_gpio_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned int mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sgc->irqmask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	sa1100_update_edge_regs(sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret = sa11x0_gpio_set_wake(d->hwirq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			sgc->irqwake |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			sgc->irqwake &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * This is for GPIO IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct irq_chip sa1100_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.name		= "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.irq_ack	= sa1100_gpio_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.irq_mask	= sa1100_gpio_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.irq_unmask	= sa1100_gpio_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.irq_set_type	= sa1100_gpio_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.irq_set_wake	= sa1100_gpio_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		unsigned int irq, irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct sa1100_gpio_chip *sgc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	irq_set_chip_data(irq, sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.map = sa1100_gpio_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct irq_domain *sa1100_gpio_irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * IRQ 0-11 (GPIO) handler.  We enter here with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * and call the handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void sa1100_gpio_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	unsigned int irq, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	void __iomem *gedr = sgc->membase + R_GEDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mask = readl_relaxed(gedr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 * clear down all currently active IRQ sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 * We will be processing them all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		writel_relaxed(mask, gedr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		irq = sgc->irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			if (mask & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			mask >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		} while (mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		mask = readl_relaxed(gedr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	} while (mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int sa1100_gpio_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * Set the appropriate edges for wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * Clear any pending GPIO interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		       sgc->membase + R_GEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void sa1100_gpio_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	sa1100_update_edge_regs(&sa1100_gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct syscore_ops sa1100_gpio_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.suspend	= sa1100_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.resume		= sa1100_gpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int __init sa1100_gpio_init_devicefs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	register_syscore_ops(&sa1100_gpio_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) device_initcall(sa1100_gpio_init_devicefs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const int sa1100_gpio_irqs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Install handlers for GPIO 0-10 edge detect interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	IRQ_GPIO0_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	IRQ_GPIO1_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	IRQ_GPIO2_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	IRQ_GPIO3_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	IRQ_GPIO4_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	IRQ_GPIO5_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	IRQ_GPIO6_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	IRQ_GPIO7_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	IRQ_GPIO8_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	IRQ_GPIO9_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	IRQ_GPIO10_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* Install handler for GPIO 11-27 edge detect interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	IRQ_GPIO11_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void __init sa1100_init_gpio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* clear all GPIO edge detects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	writel_relaxed(0, sgc->membase + R_GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	writel_relaxed(0, sgc->membase + R_GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	writel_relaxed(-1, sgc->membase + R_GEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			28, IRQ_GPIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			&sa1100_gpio_irqdomain_ops, sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 						 sa1100_gpio_handler, sgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }