^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "../pinctrl/core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../pinctrl/pinctrl-rockchip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIO_MAX_PINS (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct rockchip_gpio_regs gpio_regs_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .port_dr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .port_ddr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .int_en = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .int_mask = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .int_type = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .int_polarity = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .int_status = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .int_rawstatus = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .debounce = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .port_eoi = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .ext_port = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct rockchip_gpio_regs gpio_regs_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .port_dr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .port_ddr = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .int_en = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .int_mask = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .int_type = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .int_polarity = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .int_bothedge = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .int_status = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .int_rawstatus = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .debounce = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .dbclk_div_en = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .dbclk_div_con = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .port_eoi = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ext_port = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .version_id = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void gpio_writel_v2(u32 val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel((val & 0xffff) | 0xffff0000, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel((val >> 16) | 0xffff0000, reg + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline u32 gpio_readl_v2(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return readl(reg + 0x4) << 16 | readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *reg = bank->reg_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (bank->gpio_type == GPIO_TYPE_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gpio_writel_v2(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *reg = bank->reg_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (bank->gpio_type == GPIO_TYPE_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) value = gpio_readl_v2(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) value = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 bit, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *reg = bank->reg_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (bank->gpio_type == GPIO_TYPE_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data = BIT(bit % 16) | BIT(bit % 16 + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data = BIT(bit % 16 + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(data, bit >= 16 ? reg + 0x4 : reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) data |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 bit, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *reg = bank->reg_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (bank->gpio_type == GPIO_TYPE_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) data = readl(bit >= 16 ? reg + 0x4 : reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data >>= bit % 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data >>= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return data & (0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int rockchip_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int rockchip_gpio_set_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 data = input ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) data = readl(bank->reg_base + bank->gpio_regs->ext_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) data >>= offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) data &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct rockchip_gpio_regs *reg = bank->gpio_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long flags, div_reg, freq, max_debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool div_debounce_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int cur_div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u64 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) div_debounce_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) freq = clk_get_rate(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if ((unsigned long)debounce > max_debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) div = debounce * freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) div_debounce_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Only the v1 needs to configure div_en and div_con for dbclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (debounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (div_debounce_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Configure the max debounce from consumers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cur_div_reg = readl(bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg->dbclk_div_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (cur_div_reg < div_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(div_reg, bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg->dbclk_div_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rockchip_gpio_writel_bit(bank, offset, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg->dbclk_div_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (div_debounce_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) rockchip_gpio_writel_bit(bank, offset, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg->dbclk_div_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Enable or disable dbclk at last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (div_debounce_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk_prepare_enable(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_disable_unprepare(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int rockchip_gpio_direction_input(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return rockchip_gpio_set_direction(gc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int rockchip_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) rockchip_gpio_set(gc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return rockchip_gpio_set_direction(gc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * gpiolib set_config callback function. The setting of the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * mux function as 'gpio output' will be handled by the pinctrl subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum pin_config_param param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Rockchip's gpio could only support up to one period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * of the debounce clock(pclk), which is far away from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * satisftying the requirement, as pclk is usually near
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * 100MHz shared by all peripherals. So the fact is it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * has crippled debounce capability could only be useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * to prevent any spurious glitches from waking up the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * if the gpio is conguired as wakeup interrupt source. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * still return -ENOTSUPP as before, to make sure the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * of gpiod_set_debounce won't change its behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rockchip_gpio_set_debounce(gc, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * and a virtual IRQ, if not already present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!bank->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) virq = irq_create_mapping(bank->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return (virq) ? : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct gpio_chip rockchip_gpiolib_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .set = rockchip_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .get = rockchip_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .get_direction = rockchip_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .direction_input = rockchip_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .direction_output = rockchip_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .set_config = rockchip_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .to_irq = rockchip_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void rockchip_irq_demux(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) while (pend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int irq, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) irq = __ffs(pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pend &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) virq = irq_find_mapping(bank->domain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(bank->dev, "unmapped irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(bank->dev, "handling irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Triggering IRQ on both rising and falling edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * needs manual intervention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (bank->toggle_edge_mode & BIT(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 data, data_old, polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) data = readl_relaxed(bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bank->gpio_regs->ext_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) polarity = readl_relaxed(bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bank->gpio_regs->int_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (data & BIT(irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) polarity &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) polarity |= BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bank->gpio_regs->int_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) data_old = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) data = readl_relaxed(bank->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) bank->gpio_regs->ext_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } while ((data & BIT(irq)) != (data_old & BIT(irq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct rockchip_pin_bank *bank = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rockchip_gpio_writel_bit(bank, d->hwirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bank->gpio_regs->port_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) raw_spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (bank->gpio_type == GPIO_TYPE_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bank->toggle_edge_mode &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rockchip_gpio_writel_bit(bank, d->hwirq, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bank->gpio_regs->int_bothedge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) bank->toggle_edge_mode |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) level |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Determine gpio state. If 1 next interrupt should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * falling otherwise rising.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) data = readl(bank->reg_base + bank->gpio_regs->ext_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (data & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) polarity &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) bank->toggle_edge_mode &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) level |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bank->toggle_edge_mode &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) level |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) polarity &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bank->toggle_edge_mode &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) level &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bank->toggle_edge_mode &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) level &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) polarity &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) raw_spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void rockchip_irq_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct rockchip_pin_bank *bank = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void rockchip_irq_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct rockchip_pin_bank *bank = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void rockchip_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) irq_gc_mask_clr_bit(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void rockchip_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) irq_gc_mask_set_bit(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!bank->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_warn(bank->dev, "could not init irq domain for bank %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bank->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "rockchip_gpio_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bank->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) irq_domain_remove(bank->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) gc = irq_get_domain_generic_chip(bank->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (bank->gpio_type == GPIO_TYPE_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) gc->reg_writel = gpio_writel_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) gc->reg_readl = gpio_readl_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gc->reg_base = bank->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) gc->private = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) gc->wake_enabled = IRQ_MSK(bank->nr_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Linux assumes that all interrupts start out disabled/masked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * Our driver only uses the concept of masked and always keeps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * things enabled, so for us that's all masked and all enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) gc->mask_cache = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) irq_set_chained_handler_and_data(bank->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) rockchip_irq_demux, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bank->gpio_chip = rockchip_gpiolib_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) gc = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) gc->base = bank->pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) gc->ngpio = bank->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gc->label = bank->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) gc->parent = bank->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!gc->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) gc->base = GPIO_MAX_PINS * bank->bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) gc->ngpio = GPIO_MAX_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!gc->label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) gc->label = kasprintf(GFP_KERNEL, "gpio%d", bank->bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!gc->label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = gpiochip_add_data(gc, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gc->label, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = rockchip_interrupts_register(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) gpiochip_remove(&bank->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void rockchip_gpio_get_ver(struct rockchip_pin_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int id = readl(bank->reg_base + gpio_regs_v2.version_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* If not gpio v2, that is default to v1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) bank->gpio_regs = &gpio_regs_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) bank->gpio_type = GPIO_TYPE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bank->gpio_regs = &gpio_regs_v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) bank->gpio_type = GPIO_TYPE_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct rockchip_pin_bank *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct rockchip_pinctrl *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct rockchip_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int i, found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) bank = info->ctrl->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (bank->bank_num == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return found ? bank : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int rockchip_gpio_of_get_bank_id(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int bank_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bank_id = of_alias_get_id(dev->of_node, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (bank_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bank_id = gpio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return bank_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int rockchip_gpio_acpi_get_bank_id(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long bank_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) const char *uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uid = acpi_device_uid(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!uid || !(*uid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(dev, "Cannot retrieve UID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = kstrtoul(uid, 0, &bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return !ret ? bank_id : -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int rockchip_gpio_acpi_get_bank_id(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int rockchip_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct pinctrl_dev *pctldev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct rockchip_pin_bank *bank = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int bank_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bank_id = rockchip_gpio_acpi_get_bank_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (bank_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bank_id = rockchip_gpio_of_get_bank_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (bank_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return bank_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!ACPI_COMPANION(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct device_node *pctlnp = of_get_parent(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pctldev = of_pinctrl_get(pctlnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) bank = rockchip_gpio_find_bank(pctldev, bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) bank->bank_num = bank_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) bank->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (IS_ERR(bank->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return PTR_ERR(bank->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bank->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (bank->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return bank->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) raw_spin_lock_init(&bank->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!ACPI_COMPANION(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) bank->clk = devm_clk_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (IS_ERR(bank->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) bank->clk = of_clk_get(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (IS_ERR(bank->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(dev, "fail to get apb clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return PTR_ERR(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bank->db_clk = devm_clk_get(dev, "db");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (IS_ERR(bank->db_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) bank->db_clk = of_clk_get(dev->of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (IS_ERR(bank->db_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bank->db_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) clk_prepare_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) clk_prepare_enable(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rockchip_gpio_get_ver(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Prevent clashes with a deferred output setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * being added right at this moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_lock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = rockchip_gpiolib_register(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_err(bank->dev, "Failed to register gpio %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!device_property_read_bool(bank->dev, "gpio-ranges") && pctldev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct gpio_chip *gc = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) gc->base, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(bank->dev, "Failed to add pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) while (!list_empty(&bank->deferred_pins)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct rockchip_pin_deferred *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cfg = list_first_entry(&bank->deferred_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct rockchip_pin_deferred, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) list_del(&cfg->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) switch (cfg->param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cfg->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mutex_unlock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) platform_set_drvdata(pdev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_info(dev, "probed %pfw\n", dev_fwnode(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_unlock(&bank->deferred_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) clk_disable_unprepare(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) clk_disable_unprepare(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int rockchip_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) clk_disable_unprepare(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) clk_disable_unprepare(bank->db_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) gpiochip_remove(&bank->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct of_device_id rockchip_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { .compatible = "rockchip,gpio-bank", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { .compatible = "rockchip,rk3188-gpio-bank0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct platform_driver rockchip_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .probe = rockchip_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .remove = rockchip_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .name = "rockchip-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .of_match_table = rockchip_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int __init rockchip_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return platform_driver_register(&rockchip_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) postcore_initcall(rockchip_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void __exit rockchip_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) platform_driver_unregister(&rockchip_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) module_exit(rockchip_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MODULE_DESCRIPTION("Rockchip gpio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_ALIAS("platform:rockchip-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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