Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * regmap based generic GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2020 Michael Walle <michael@walle.cc>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) struct gpio_regmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	int reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	int ngpio_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	unsigned int reg_dat_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int reg_set_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int reg_clr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned int reg_dir_in_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int reg_dir_out_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			      unsigned int offset, unsigned int *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			      unsigned int *mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	void *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static unsigned int gpio_regmap_addr(unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (addr == GPIO_REGMAP_ADDR_ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int gpio_regmap_simple_xlate(struct gpio_regmap *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				    unsigned int base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				    unsigned int *reg, unsigned int *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int line = offset % gpio->ngpio_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int stride = offset / gpio->ngpio_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	*reg = base + stride * gpio->reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	*mask = BIT(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct gpio_regmap *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int base, val, reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* we might not have an output register if we are input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (gpio->reg_dat_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		base = gpio_regmap_addr(gpio->reg_dat_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		base = gpio_regmap_addr(gpio->reg_set_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ret = gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	ret = regmap_read(gpio->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void gpio_regmap_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			    int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct gpio_regmap *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned int base = gpio_regmap_addr(gpio->reg_set_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned int reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		regmap_update_bits(gpio->regmap, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		regmap_update_bits(gpio->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void gpio_regmap_set_with_clear(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				       unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct gpio_regmap *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int base, reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		base = gpio_regmap_addr(gpio->reg_set_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		base = gpio_regmap_addr(gpio->reg_clr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	regmap_write(gpio->regmap, reg, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int gpio_regmap_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				     unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct gpio_regmap *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned int base, val, reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int invert, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (gpio->reg_dir_out_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		base = gpio_regmap_addr(gpio->reg_dir_out_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		invert = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	} else if (gpio->reg_dir_in_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		base = gpio_regmap_addr(gpio->reg_dir_in_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		invert = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ret = gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ret = regmap_read(gpio->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!!(val & mask) ^ invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int gpio_regmap_set_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				     unsigned int offset, bool output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct gpio_regmap *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int base, val, reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int invert, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (gpio->reg_dir_out_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		base = gpio_regmap_addr(gpio->reg_dir_out_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		invert = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	} else if (gpio->reg_dir_in_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		base = gpio_regmap_addr(gpio->reg_dir_in_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		invert = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret = gpio->reg_mask_xlate(gpio, base, offset, &reg, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		val = output ? 0 : mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		val = output ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return regmap_update_bits(gpio->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int gpio_regmap_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				       unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return gpio_regmap_set_direction(chip, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int gpio_regmap_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 					unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	gpio_regmap_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return gpio_regmap_set_direction(chip, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void gpio_regmap_set_drvdata(struct gpio_regmap *gpio, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	gpio->driver_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EXPORT_SYMBOL_GPL(gpio_regmap_set_drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return gpio->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL_GPL(gpio_regmap_get_drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * gpio_regmap_register() - Register a generic regmap GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * @config: configuration for gpio_regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * Return: A pointer to the registered gpio_regmap or ERR_PTR error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct gpio_regmap *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (!config->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!config->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* we need at least one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!config->reg_dat_base && !config->reg_set_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* if we have a direction register we need both input and output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if ((config->reg_dir_out_base || config->reg_dir_in_base) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	    (!config->reg_dat_base || !config->reg_set_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* we don't support having both registers simultaneously for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (config->reg_dir_out_base && config->reg_dir_in_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	gpio = kzalloc(sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	gpio->parent = config->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	gpio->regmap = config->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	gpio->ngpio_per_reg = config->ngpio_per_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	gpio->reg_stride = config->reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	gpio->reg_mask_xlate = config->reg_mask_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	gpio->reg_dat_base = config->reg_dat_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	gpio->reg_set_base = config->reg_set_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	gpio->reg_clr_base = config->reg_clr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	gpio->reg_dir_in_base = config->reg_dir_in_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	gpio->reg_dir_out_base = config->reg_dir_out_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* if not set, assume there is only one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!gpio->ngpio_per_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		gpio->ngpio_per_reg = config->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* if not set, assume they are consecutive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (!gpio->reg_stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		gpio->reg_stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (!gpio->reg_mask_xlate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		gpio->reg_mask_xlate = gpio_regmap_simple_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	chip = &gpio->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	chip->parent = config->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	chip->ngpio = config->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	chip->names = config->names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	chip->label = config->label ?: dev_name(config->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * If our regmap is fast_io we should probably set can_sleep to false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * Right now, the regmap doesn't save this property, nor is there any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * access function for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * The only regmap type which uses fast_io is regmap-mmio. For now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * assume a safe default of true here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	chip->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	chip->get = gpio_regmap_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (gpio->reg_set_base && gpio->reg_clr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		chip->set = gpio_regmap_set_with_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	else if (gpio->reg_set_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		chip->set = gpio_regmap_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (gpio->reg_dir_in_base || gpio->reg_dir_out_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		chip->get_direction = gpio_regmap_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		chip->direction_input = gpio_regmap_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		chip->direction_output = gpio_regmap_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = gpiochip_add_data(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		goto err_free_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (config->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = gpiochip_irqchip_add_domain(chip, config->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			goto err_remove_gpiochip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_remove_gpiochip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	gpiochip_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_free_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	kfree(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) EXPORT_SYMBOL_GPL(gpio_regmap_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * gpio_regmap_unregister() - Unregister a generic regmap GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * @gpio: gpio_regmap device to unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void gpio_regmap_unregister(struct gpio_regmap *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	gpiochip_remove(&gpio->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	kfree(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) EXPORT_SYMBOL_GPL(gpio_regmap_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void devm_gpio_regmap_unregister(struct device *dev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	gpio_regmap_unregister(*(struct gpio_regmap **)res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  * devm_gpio_regmap_register() - resource managed gpio_regmap_register()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * @dev: device that is registering this GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * @config: configuration for gpio_regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * Managed gpio_regmap_register(). For generic regmap GPIO device registered by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  * this function, gpio_regmap_unregister() is automatically called on driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * detach. See gpio_regmap_register() for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * Return: A pointer to the registered gpio_regmap or ERR_PTR error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct gpio_regmap *devm_gpio_regmap_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					      const struct gpio_regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct gpio_regmap **ptr, *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ptr = devres_alloc(devm_gpio_regmap_unregister, sizeof(*ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	gpio = gpio_regmap_register(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		*ptr = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		devres_add(dev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		devres_free(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EXPORT_SYMBOL_GPL(devm_gpio_regmap_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_DESCRIPTION("GPIO generic regmap driver core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_LICENSE("GPL");