^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gpio-reg: single register individually fixed-direction GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/gpio-reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct gpio_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const int *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (r->direction & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) gc->set(gc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val, mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spin_lock_irqsave(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val = r->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) r->out = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(val, r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spin_unlock_irqrestore(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 val, mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (r->direction & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * double-read the value, some registers latch after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * first read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) readl_relaxed(r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val = readl_relaxed(r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = r->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock_irqsave(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) r->out = (r->out & ~*mask) | (*bits & *mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel_relaxed(r->out, r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_unlock_irqrestore(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int irq = r->irqs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (irq >= 0 && r->irqdomain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq = irq_find_mapping(r->irqdomain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * gpio_reg_init - add a fixed in/out register as gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @dev: optional struct device associated with this register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @base: start gpio number, or -1 to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @num: number of GPIOs, maximum 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @label: GPIO chip label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @def_out: initial GPIO output value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @names: array of %num strings describing each GPIO signal or %NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @irqdom: irq domain or %NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @irqs: array of %num ints describing the interrupt mapping for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * GPIO signal, or %NULL. If @irqdom is %NULL, then this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * describes the Linux interrupt number, otherwise it describes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the hardware interrupt number in the specified irq domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Add a single-register GPIO device containing up to 32 GPIO signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * where each GPIO has a fixed input or output configuration. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * input GPIOs are assumed to be readable from the register, and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * then after a double-read. Output values are assumed not to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * readable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int base, int num, const char *label, u32 direction, u32 def_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *const *names, struct irq_domain *irqdom, const int *irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct gpio_reg *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) r = kzalloc(sizeof(*r), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_lock_init(&r->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) r->gc.label = label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) r->gc.get_direction = gpio_reg_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) r->gc.direction_input = gpio_reg_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) r->gc.direction_output = gpio_reg_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) r->gc.set = gpio_reg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) r->gc.get = gpio_reg_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) r->gc.set_multiple = gpio_reg_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) r->gc.to_irq = gpio_reg_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) r->gc.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) r->gc.ngpio = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) r->gc.names = names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) r->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) r->out = def_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) r->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) r->irqs = irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = devm_gpiochip_add_data(dev, &r->gc, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = gpiochip_add_data(&r->gc, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret ? ERR_PTR(ret) : &r->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int gpio_reg_resume(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct gpio_reg *r = to_gpio_reg(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) spin_lock_irqsave(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel_relaxed(r->out, r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_unlock_irqrestore(&r->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags