^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RDA Micro GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 RDA Micro Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Manivannan Sadhasivam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RDA_GPIO_OEN_VAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RDA_GPIO_OEN_SET_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RDA_GPIO_OEN_SET_IN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RDA_GPIO_VAL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RDA_GPIO_SET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RDA_GPIO_CLR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RDA_GPIO_INT_CTRL_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RDA_GPIO_INT_CTRL_CLR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RDA_GPIO_INT_CLR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RDA_GPIO_INT_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RDA_GPIO_IRQ_RISE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RDA_GPIO_IRQ_FALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RDA_GPIO_DEBOUCE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RDA_GPIO_LEVEL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RDA_GPIO_IRQ_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Each bank consists of 32 GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RDA_GPIO_BANK_NR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct rda_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base = rda_gpio->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) spin_lock_irqsave(&rda_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tmp = readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) tmp |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tmp &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(tmp, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spin_unlock_irqrestore(&rda_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void rda_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *base = rda_gpio->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void rda_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *base = rda_gpio->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Set rising edge trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Switch to edge trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Set falling edge trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Switch to edge trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Set both edge trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Switch to edge trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Set high level trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Switch to level trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Set low level trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Switch to level trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void rda_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 trigger = irqd_get_trigger_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rda_gpio_set_irq(chip, offset, trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = rda_gpio_set_irq(chip, offset, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void rda_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct irq_chip *ic = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 n, girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) chained_irq_enter(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Only lower 8 bits are capable of generating interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) status &= RDA_GPIO_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) girq = irq_find_mapping(chip->irq.domain, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) generic_handle_irq(girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) chained_irq_exit(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int rda_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct rda_gpio *rda_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!rda_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = device_property_read_u32(dev, "ngpios", &ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Not all ports have interrupt capability. For instance, on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * RDA8810PL, GPIOC doesn't support interrupt. So we must handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * those also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rda_gpio->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rda_gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (IS_ERR(rda_gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR(rda_gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock_init(&rda_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = bgpio_init(&rda_gpio->chip, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rda_gpio->base + RDA_GPIO_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rda_gpio->base + RDA_GPIO_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rda_gpio->base + RDA_GPIO_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rda_gpio->base + RDA_GPIO_OEN_SET_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) BGPIOF_READ_OUTPUT_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "bgpio_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rda_gpio->chip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rda_gpio->chip.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rda_gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) rda_gpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rda_gpio->chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (rda_gpio->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rda_gpio->irq_chip.name = "rda-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) girq = &rda_gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) girq->chip = &rda_gpio->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) girq->parent_handler = rda_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) girq->parent_handler_data = rda_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) girq->parents = devm_kcalloc(dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) girq->parents[0] = rda_gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) platform_set_drvdata(pdev, rda_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct of_device_id rda_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .compatible = "rda,8810pl-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_DEVICE_TABLE(of, rda_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct platform_driver rda_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .probe = rda_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "rda-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .of_match_table = rda_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DESCRIPTION("RDA Micro GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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