^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R-Car GPIO Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct gpio_rcar_bank_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 iointsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 inoutsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 outdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 posneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 edglevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 bothedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_rcar_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) atomic_t wakeup_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool has_outdtsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool has_both_edge_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct gpio_rcar_bank_info bank_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INOUTSEL 0x04 /* General Input/Output Switching Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OUTDT 0x08 /* General Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INDT 0x0c /* General Input Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define INTDT 0x10 /* Interrupt Display Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define INTCLR 0x14 /* Interrupt Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define INTMSK 0x18 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EDGLEVEL 0x24 /* Edge/level Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OUTDTSEL 0x40 /* Output Data Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RCAR_MAX_GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ioread32(p->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite32(value, p->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int bit, bool value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 tmp = gpio_rcar_read(p, offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tmp &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) gpio_rcar_write(p, offs, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void gpio_rcar_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct gpio_rcar_priv *p = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void gpio_rcar_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct gpio_rcar_priv *p = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool active_high_rising_edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool level_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool both)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* follow steps in the GPIO documentation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * "Setting Edge-Sensitive Interrupt Input Mode" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * "Setting Level-Sensitive Interrupt Input Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Configure positive or negative logic in POSNEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Configure edge or level trigger in EDGLEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Select one edge or both edges in BOTHEDGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (p->has_both_edge_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Select "Interrupt Input Mode" in IOINTSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Write INTCLR in case of edge trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!level_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) gpio_rcar_write(p, INTCLR, BIT(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_rcar_priv *p = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!p->has_both_edge_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct gpio_rcar_priv *p = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (p->irq_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) error = irq_set_irq_wake(p->irq_parent, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) p->irq_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) p->irq_parent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) atomic_inc(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) atomic_dec(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct gpio_rcar_priv *p = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int offset, irqs_handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) while ((pending = gpio_rcar_read(p, INTDT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) gpio_rcar_read(p, INTMSK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) offset = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gpio_rcar_write(p, INTCLR, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) irqs_handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* follow steps in the GPIO documentation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * "Setting General Output Mode" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * "Setting General Input Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Configure positive logic in POSNEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) gpio_rcar_modify_bit(p, POSNEG, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Select "General Input/Output Mode" in IOINTSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Select Input Mode or Output Mode in INOUTSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Select General Output Register to output data in OUTDTSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (p->has_outdtsel && output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) error = pm_runtime_get_sync(p->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pm_runtime_put(p->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) error = pinctrl_gpio_request(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pm_runtime_put(p->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pinctrl_gpio_free(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Set the GPIO as an input to ensure that the next GPIO request won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * drive the GPIO pin as an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) gpio_rcar_config_general_input_output_mode(chip, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pm_runtime_put(p->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) gpio_rcar_config_general_input_output_mode(chip, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* testing on r8a7790 shows that INDT does not show correct pin state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * when configured as output, so use OUTDT in case of output pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gpio_rcar_modify_bit(p, OUTDT, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct gpio_rcar_priv *p = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 val, bankmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (chip->valid_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bankmask &= chip->valid_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!bankmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = gpio_rcar_read(p, OUTDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val &= ~bankmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val |= (bankmask & bits[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gpio_rcar_write(p, OUTDT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* write GPIO value to output before selecting output mode of pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gpio_rcar_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) gpio_rcar_config_general_input_output_mode(chip, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct gpio_rcar_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bool has_outdtsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bool has_both_edge_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .has_outdtsel = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .has_both_edge_trigger = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .has_outdtsel = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .has_both_edge_trigger = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct of_device_id gpio_rcar_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .compatible = "renesas,gpio-r8a7743",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* RZ/G1 GPIO is identical to R-Car Gen2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .compatible = "renesas,gpio-r8a7790",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .compatible = "renesas,gpio-r8a7791",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .compatible = "renesas,gpio-r8a7792",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .compatible = "renesas,gpio-r8a7793",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .compatible = "renesas,gpio-r8a7794",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .compatible = "renesas,gpio-r8a7795",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Gen3 GPIO is identical to Gen2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .compatible = "renesas,gpio-r8a7796",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Gen3 GPIO is identical to Gen2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .compatible = "renesas,rcar-gen1-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .data = &gpio_rcar_info_gen1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .compatible = "renesas,rcar-gen2-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .compatible = "renesas,rcar-gen3-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Gen3 GPIO is identical to Gen2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .data = &gpio_rcar_info_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .compatible = "renesas,gpio-rcar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .data = &gpio_rcar_info_gen1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct device_node *np = p->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) const struct gpio_rcar_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) info = of_device_get_match_data(p->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) p->has_outdtsel = info->has_outdtsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) p->has_both_edge_trigger = info->has_both_edge_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *npins, RCAR_MAX_GPIO_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *npins = RCAR_MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int gpio_rcar_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct gpio_rcar_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct resource *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct gpio_chip *gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) p->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spin_lock_init(&p->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Get device configuration from DT node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = gpio_rcar_parse_dt(p, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(dev, "missing IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) p->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (IS_ERR(p->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = PTR_ERR(p->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) gpio_chip = &p->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) gpio_chip->request = gpio_rcar_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) gpio_chip->free = gpio_rcar_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) gpio_chip->get_direction = gpio_rcar_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gpio_chip->direction_input = gpio_rcar_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) gpio_chip->get = gpio_rcar_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) gpio_chip->direction_output = gpio_rcar_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) gpio_chip->set = gpio_rcar_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) gpio_chip->set_multiple = gpio_rcar_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) gpio_chip->label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gpio_chip->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gpio_chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) gpio_chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) gpio_chip->ngpio = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) irq_chip = &p->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) irq_chip->name = "gpio-rcar";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) irq_chip->parent_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) irq_chip->irq_mask = gpio_rcar_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) irq_chip->irq_unmask = gpio_rcar_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) irq_chip->irq_set_type = gpio_rcar_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) girq = &gpio_chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) girq->chip = irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = gpiochip_add_data(gpio_chip, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(dev, "failed to add GPIO controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) p->irq_parent = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) IRQF_SHARED, name, p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_info(dev, "driving %d GPIOs\n", npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gpiochip_remove(gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int gpio_rcar_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) gpiochip_remove(&p->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int gpio_rcar_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct gpio_rcar_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (p->has_both_edge_trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (atomic_read(&p->wakeup_path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) device_set_wakeup_path(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int gpio_rcar_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct gpio_rcar_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* I/O pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!(p->bank_info.iointsel & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (p->bank_info.inoutsel & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gpio_rcar_direction_output(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &p->gpio_chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) !!(p->bank_info.outdt & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) gpio_rcar_direction_input(&p->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Interrupt pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) gpio_rcar_config_interrupt_input_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) !(p->bank_info.posneg & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) !(p->bank_info.edglevel & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) !!(p->bank_info.bothedge & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (p->bank_info.intmsk & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gpio_rcar_write(p, MSKCLR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #endif /* CONFIG_PM_SLEEP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct platform_driver gpio_rcar_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .probe = gpio_rcar_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .remove = gpio_rcar_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "gpio_rcar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pm = &gpio_rcar_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .of_match_table = of_match_ptr(gpio_rcar_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) module_platform_driver(gpio_rcar_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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