^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/plat-pxa/gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Generic PXA GPIO handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Created: Jun 15, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * one set of registers. The register offsets are organized below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * GPLR GPDR GPSR GPCR GRER GFER GEDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * BANK 3 is only available on PXA27x and later processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * BANK 4 and 5 are only available on PXA935, PXA1928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * BANK 6 is only available on PXA1928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPLR_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPDR_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPSR_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPCR_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GRER_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GFER_OFFSET 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GEDR_OFFSET 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GAFR_OFFSET 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int pxa_last_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pxa_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long irq_edge_rise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long irq_edge_fall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long saved_gplr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long saved_gpdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long saved_grer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long saved_gfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pxa_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pxa_gpio_bank *banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int irq0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int (*set_wake)(unsigned int gpio, unsigned int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum pxa_gpio_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PXA25X_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PXA26X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PXA27X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PXA3XX_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PXA93X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MMP_GPIO = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MMP2_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PXA1928_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pxa_gpio_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum pxa_gpio_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int gpio_nums;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static DEFINE_SPINLOCK(gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct pxa_gpio_chip *pxa_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static enum pxa_gpio_type gpio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct pxa_gpio_id pxa25x_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .type = PXA25X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .gpio_nums = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct pxa_gpio_id pxa26x_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .type = PXA26X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .gpio_nums = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct pxa_gpio_id pxa27x_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .type = PXA27X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .gpio_nums = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct pxa_gpio_id pxa3xx_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .type = PXA3XX_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .gpio_nums = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct pxa_gpio_id pxa93x_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .type = PXA93X_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .gpio_nums = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct pxa_gpio_id mmp_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .type = MMP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .gpio_nums = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct pxa_gpio_id mmp2_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .type = MMP2_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .gpio_nums = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct pxa_gpio_id pxa1928_id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .type = PXA1928_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .gpio_nums = 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define for_each_gpio_bank(i, b, pc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return pxa_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct pxa_gpio_chip *p = gpiochip_get_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return bank->regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return chip_to_pxachip(c)->banks + gpio / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline int gpio_is_pxa_type(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return (type & MMP_GPIO) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline int gpio_is_mmp_type(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return (type & MMP_GPIO) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * as well as their Alternate Function value being '1' for GPIO in GAFRx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline int __gpio_is_inverted(int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * function of a GPIO, and GPDRx cannot be altered once configured. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * is attributed as "occupied" here (I know this terminology isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * accurate, you are welcome to propose a better one :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long gafr = 0, gpdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ret, af = 0, dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) base = gpio_bank_base(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) gpdr = readl_relaxed(base + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (gpio_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case PXA25X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case PXA26X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case PXA27X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gafr = readl_relaxed(base + GAFR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dir = gpdr & GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (__gpio_is_inverted(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = (af != 1) || (dir == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = (af != 0) || (dir != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = gpdr & GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int pxa_irq_to_gpio(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct pxa_gpio_chip *pchip = pxa_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int irq_gpio0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (irq_gpio0 > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return irq - irq_gpio0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return irq_gpio0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static bool pxa_gpio_has_pinctrl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (gpio_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case PXA3XX_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case MMP2_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return irq_find_mapping(pchip->irqdomain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __iomem *base = gpio_bank_base(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t value, mask = GPIO_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (pxa_gpio_has_pinctrl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) value = readl_relaxed(base + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (__gpio_is_inverted(chip->base + offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel_relaxed(value, base + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int pxa_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void __iomem *base = gpio_bank_base(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint32_t tmp, mask = GPIO_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pxa_gpio_has_pinctrl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tmp = readl_relaxed(base + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (__gpio_is_inverted(chip->base + offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel_relaxed(tmp, base + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void __iomem *base = gpio_bank_base(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 gplr = readl_relaxed(base + GPLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return !!(gplr & GPIO_bit(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void __iomem *base = gpio_bank_base(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) writel_relaxed(GPIO_bit(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) base + (value ? GPSR_OFFSET : GPCR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int pxa_gpio_of_xlate(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const struct of_phandle_args *gpiospec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (gpiospec->args[0] > pxa_last_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *flags = gpiospec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return gpiospec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct device_node *np, void __iomem *regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct pxa_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!pchip->banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pchip->chip.label = "gpio-pxa";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pchip->chip.direction_input = pxa_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pchip->chip.direction_output = pxa_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pchip->chip.get = pxa_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pchip->chip.set = pxa_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pchip->chip.to_irq = pxa_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pchip->chip.ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pchip->chip.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pchip->chip.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pchip->chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pchip->chip.of_xlate = pxa_gpio_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pchip->chip.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bank = pchip->banks + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bank->regbase = regbase + BANK_OFF(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return gpiochip_add_data(&pchip->chip, pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Update only those GRERx and GFERx edge detection register bits if those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * bits are set in c->irq_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline void update_edge_detect(struct pxa_gpio_bank *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) uint32_t grer, gfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) grer |= c->irq_edge_rise & c->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) gfer |= c->irq_edge_fall & c->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel_relaxed(grer, c->regbase + GRER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) writel_relaxed(gfer, c->regbase + GFER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long gpdr, mask = GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (type == IRQ_TYPE_PROBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Don't mess with enabled GPIOs using preconfigured edges or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * GPIOs set to alternate function or to output during probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (__gpio_is_occupied(pchip, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (__gpio_is_inverted(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) c->irq_edge_rise |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) c->irq_edge_rise &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) c->irq_edge_fall |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) c->irq_edge_fall &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) update_edge_detect(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int loop, gpio, n, handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long gedr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct pxa_gpio_chip *pchip = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct pxa_gpio_bank *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for_each_gpio_bank(gpio, c, pchip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gedr = gedr & c->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for_each_set_bit(n, &gedr, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) irq_find_mapping(pchip->irqdomain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) gpio + n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) handled += loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } while (loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct pxa_gpio_chip *pchip = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (in_irq == pchip->irq0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else if (in_irq == pchip->irq1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pr_err("%s() unknown irq %d\n", __func__, in_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void pxa_ack_muxed_gpio(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void pxa_mask_muxed_gpio(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint32_t grer, gfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) b->irq_mask &= ~GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel_relaxed(grer, base + GRER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) writel_relaxed(gfer, base + GFER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (pchip->set_wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return pchip->set_wake(gpio, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void pxa_unmask_muxed_gpio(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) c->irq_mask |= GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) update_edge_detect(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct irq_chip pxa_muxed_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .irq_ack = pxa_ack_muxed_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .irq_mask = pxa_mask_muxed_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .irq_unmask = pxa_unmask_muxed_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .irq_set_type = pxa_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .irq_set_wake = pxa_gpio_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int pxa_gpio_nums(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct platform_device_id *id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) switch (pxa_id->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case PXA25X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case PXA26X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case PXA27X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case PXA3XX_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case PXA93X_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case MMP_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case MMP2_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case PXA1928_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) gpio_type = pxa_id->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) count = pxa_id->gpio_nums - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) irq_set_chip_data(irq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct irq_domain_ops pxa_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .map = pxa_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct of_device_id pxa_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int pxa_gpio_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct pxa_gpio_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int nr_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) const struct pxa_gpio_id *gpio_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gpio_id = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) gpio_type = gpio_id->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) nr_gpios = gpio_id->gpio_nums;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pxa_last_gpio = nr_gpios - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define pxa_gpio_probe_dt(pdev, pchip) (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int pxa_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct pxa_gpio_chip *pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct pxa_gpio_bank *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct pxa_gpio_platform_data *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void __iomem *gpio_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int gpio, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int irq0 = 0, irq1 = 0, irq_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pchip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) info = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) irq_base = info->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (irq_base <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pxa_last_gpio = pxa_gpio_nums(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pchip->set_wake = info->gpio_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) irq_base = pxa_gpio_probe_dt(pdev, pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (irq_base < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!pxa_last_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pxa_last_gpio + 1, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0, &pxa_irq_domain_ops, pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!pchip->irqdomain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) || (irq_mux <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pchip->irq0 = irq0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pchip->irq1 = irq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (IS_ERR(gpio_reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return PTR_ERR(gpio_reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Initialize GPIO chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) gpio_reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* clear all GPIO edge detects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) for_each_gpio_bank(gpio, c, pchip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) writel_relaxed(0, c->regbase + GFER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel_relaxed(0, c->regbase + GRER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) writel_relaxed(~0, c->regbase + GEDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* unmask GPIO edge detect for AP side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (gpio_is_mmp_type(gpio_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (irq0 > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) irq0, pxa_gpio_direct_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "gpio-0", pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (irq1 > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) irq1, pxa_gpio_direct_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "gpio-1", pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) irq_mux, pxa_gpio_demux_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "gpio-mux", pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pxa_gpio_chip = pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct platform_device_id gpio_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { "pxa25x-gpio", (unsigned long)&pxa25x_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { "pxa26x-gpio", (unsigned long)&pxa26x_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { "pxa27x-gpio", (unsigned long)&pxa27x_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { "pxa93x-gpio", (unsigned long)&pxa93x_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { "mmp-gpio", (unsigned long)&mmp_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { "mmp2-gpio", (unsigned long)&mmp2_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { "pxa1928-gpio", (unsigned long)&pxa1928_id },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct platform_driver pxa_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .probe = pxa_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "pxa-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .id_table = gpio_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int __init pxa_gpio_legacy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return platform_driver_register(&pxa_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) postcore_initcall(pxa_gpio_legacy_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int __init pxa_gpio_dt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return platform_driver_register(&pxa_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) device_initcall(pxa_gpio_dt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int pxa_gpio_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct pxa_gpio_chip *pchip = pxa_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct pxa_gpio_bank *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) for_each_gpio_bank(gpio, c, pchip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Clear GPIO transition detect bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void pxa_gpio_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct pxa_gpio_chip *pchip = pxa_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct pxa_gpio_bank *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for_each_gpio_bank(gpio, c, pchip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* restore level with set/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define pxa_gpio_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define pxa_gpio_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct syscore_ops pxa_gpio_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .suspend = pxa_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .resume = pxa_gpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int __init pxa_gpio_sysinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) register_syscore_ops(&pxa_gpio_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) postcore_initcall(pxa_gpio_sysinit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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