Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2018 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* EIC registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SPRD_PMIC_EIC_DATA		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SPRD_PMIC_EIC_DMSK		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SPRD_PMIC_EIC_IEV		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SPRD_PMIC_EIC_IE		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SPRD_PMIC_EIC_RIS		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SPRD_PMIC_EIC_MIS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SPRD_PMIC_EIC_IC		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SPRD_PMIC_EIC_TRIG		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SPRD_PMIC_EIC_CTRL0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * The PMIC EIC controller only has one bank, and each bank now can contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * 16 EICs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPRD_PMIC_EIC_PER_BANK_NR	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SPRD_PMIC_EIC_NR		SPRD_PMIC_EIC_PER_BANK_NR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SPRD_PMIC_EIC_DATA_MASK		GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SPRD_PMIC_EIC_BIT(x)		((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SPRD_PMIC_EIC_DBNC_MASK		GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * These registers are modified under the irq bus lock and cached to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * unnecessary writes in bus_sync_unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	REG_IEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	REG_IE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	REG_TRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	CACHE_NR_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * struct sprd_pmic_eic - PMIC EIC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @chip: the gpio_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * @intc: the irq_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @map:  the regmap from the parent device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @offset: the EIC controller's offset address of the PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @reg: the array to cache the EIC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @buslock: for bus lock/sync and unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @irq: the interrupt number of the PMIC EIC conteroller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct sprd_pmic_eic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct irq_chip intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u8 reg[CACHE_NR_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct mutex buslock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				 u16 reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 shift = SPRD_PMIC_EIC_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			   BIT(shift), val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			      u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 					 unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* EICs are always input, nothing need to do here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			      int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* EICs are always input, nothing need to do here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				      unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				      unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 reg, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	value &= ~SPRD_PMIC_EIC_DBNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				    unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned long param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32 arg = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (param == PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return sprd_pmic_eic_set_debounce(chip, offset, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void sprd_pmic_eic_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	pmic_eic->reg[REG_IE] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pmic_eic->reg[REG_TRIG] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	pmic_eic->reg[REG_IE] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pmic_eic->reg[REG_TRIG] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				      unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		pmic_eic->reg[REG_IEV] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		pmic_eic->reg[REG_IEV] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		 * Will set the trigger level according to current EIC level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 * in irq_bus_sync_unlock() interface, so here nothing to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void sprd_pmic_eic_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mutex_lock(&pmic_eic->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 trigger = irqd_get_trigger_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* Set irq type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (trigger & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		state = sprd_pmic_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				     pmic_eic->reg[REG_IEV]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* Set irq unmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			     pmic_eic->reg[REG_IE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Generate trigger start pulse for debounce EIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			     pmic_eic->reg[REG_TRIG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mutex_unlock(&pmic_eic->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					 unsigned int irq, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 trigger = irq_get_trigger_type(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int state, post_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!(trigger & IRQ_TYPE_EDGE_BOTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	state = sprd_pmic_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	post_state = sprd_pmic_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (state != post_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_warn(chip->parent, "PMIC EIC level was changed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		state = post_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Set irq unmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* Generate trigger start pulse for debounce EIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct sprd_pmic_eic *pmic_eic = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct gpio_chip *chip = &pmic_eic->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u32 n, girq, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			  &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	status = val & SPRD_PMIC_EIC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	for_each_set_bit(n, &status, chip->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		/* Clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		girq = irq_find_mapping(chip->irq.domain, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		handle_nested_irq(girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		 * The PMIC EIC can only support level trigger, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 * toggle the level trigger to emulate the edge trigger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		sprd_pmic_eic_toggle_trigger(chip, girq, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int sprd_pmic_eic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct sprd_pmic_eic *pmic_eic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!pmic_eic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	mutex_init(&pmic_eic->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	pmic_eic->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (pmic_eic->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return pmic_eic->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!pmic_eic->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 					sprd_pmic_eic_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 					IRQF_ONESHOT | IRQF_NO_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 					dev_name(&pdev->dev), pmic_eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	pmic_eic->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	pmic_eic->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	pmic_eic->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	pmic_eic->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	pmic_eic->chip.request = sprd_pmic_eic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	pmic_eic->chip.free = sprd_pmic_eic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	pmic_eic->chip.set = sprd_pmic_eic_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	pmic_eic->chip.get = sprd_pmic_eic_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	pmic_eic->intc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	irq = &pmic_eic->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	irq->chip = &pmic_eic->intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	irq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	platform_set_drvdata(pdev, pmic_eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct of_device_id sprd_pmic_eic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	{ .compatible = "sprd,sc2731-eic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ /* end of list */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct platform_driver sprd_pmic_eic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.probe = sprd_pmic_eic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.name = "sprd-pmic-eic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.of_match_table	= sprd_pmic_eic_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) module_platform_driver(sprd_pmic_eic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_LICENSE("GPL v2");