^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008, 2009 Provigent Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Baruch Siach <baruch@tkos.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Data sheet: ARM DDI 0190B, September 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIODIR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPIOIS 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIOIBE 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIOIEV 0x40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPIOIE 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPIORIS 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIOMIS 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPIOIC 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PL061_GPIO_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pl061_context_save_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 gpio_is;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 gpio_ibe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 gpio_iev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 gpio_ie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pl061 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct pl061_context_save_regs csave_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (readb(pl061->base + GPIODIR) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned char gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) raw_spin_lock_irqsave(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) gpiodir = readb(pl061->base + GPIODIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) gpiodir &= ~(BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writeb(gpiodir, pl061->base + GPIODIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) raw_spin_unlock_irqrestore(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned char gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) raw_spin_lock_irqsave(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) gpiodir = readb(pl061->base + GPIODIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) gpiodir |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writeb(gpiodir, pl061->base + GPIODIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * gpio value is set again, because pl061 doesn't allow to set value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * a gpio pin before configuring it in OUT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) raw_spin_unlock_irqrestore(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return !!readb(pl061->base + (BIT(offset + 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int pl061_irq_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 gpiois, gpioibe, gpioiev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (offset < 0 || offset >= PL061_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(gc->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "trying to configure line %d for both level and edge "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "detection, choose one!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) raw_spin_lock_irqsave(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) gpioiev = readb(pl061->base + GPIOIEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gpiois = readb(pl061->base + GPIOIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gpioibe = readb(pl061->base + GPIOIBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Disable edge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) gpioibe &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Enable level detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gpiois |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Select polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gpioiev |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) gpioiev &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) polarity ? "HIGH" : "LOW");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Disable level detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gpiois &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Select both edges, setting this makes GPIOEV be ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) gpioibe |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (trigger & IRQ_TYPE_EDGE_FALLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bool rising = trigger & IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Disable level detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpiois &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Clear detection on both edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gpioibe &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Select edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (rising)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) gpioiev |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gpioiev &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rising ? "RISING" : "FALLING");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* No trigger: disable everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gpiois &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gpioibe &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) gpioiev &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) irq_set_handler_locked(d, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_warn(gc->parent, "no trigger selected for line %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writeb(gpiois, pl061->base + GPIOIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writeb(gpioibe, pl061->base + GPIOIBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writeb(gpioiev, pl061->base + GPIOIEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) raw_spin_unlock_irqrestore(&pl061->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void pl061_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pending = readb(pl061->base + GPIOMIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for_each_set_bit(offset, &pending, PL061_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) generic_handle_irq(irq_find_mapping(gc->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void pl061_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 gpioie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) raw_spin_lock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) gpioie = readb(pl061->base + GPIOIE) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writeb(gpioie, pl061->base + GPIOIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) raw_spin_unlock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void pl061_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 gpioie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) raw_spin_lock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gpioie = readb(pl061->base + GPIOIE) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writeb(gpioie, pl061->base + GPIOIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) raw_spin_unlock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * pl061_irq_ack() - ACK an edge IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @d: IRQ data for this IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * This gets called from the edge IRQ handler to ACK the edge IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * in the GPIOIC (interrupt-clear) register. For level IRQs this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * not needed: these go away when the level signal goes away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void pl061_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) raw_spin_lock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writeb(mask, pl061->base + GPIOIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) raw_spin_unlock(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct pl061 *pl061 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return irq_set_irq_wake(pl061->parent_irq, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct device *dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct pl061 *pl061;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (pl061 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pl061->base = devm_ioremap_resource(dev, &adev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (IS_ERR(pl061->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return PTR_ERR(pl061->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) raw_spin_lock_init(&pl061->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pl061->gc.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pl061->gc.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pl061->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pl061->gc.get_direction = pl061_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pl061->gc.direction_input = pl061_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pl061->gc.direction_output = pl061_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pl061->gc.get = pl061_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pl061->gc.set = pl061_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pl061->gc.ngpio = PL061_GPIO_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pl061->gc.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pl061->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pl061->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * irq_chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pl061->irq_chip.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pl061->irq_chip.irq_ack = pl061_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pl061->irq_chip.irq_mask = pl061_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pl061->irq_chip.irq_unmask = pl061_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pl061->irq_chip.irq_set_type = pl061_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writeb(0, pl061->base + GPIOIE); /* disable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq = adev->irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_warn(&adev->dev, "IRQ support disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pl061->parent_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) girq = &pl061->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) girq->chip = &pl061->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) girq->parent_handler = pl061_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) amba_set_drvdata(adev, pl061);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_info(dev, "PL061 GPIO chip registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int pl061_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct pl061 *pl061 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pl061->csave_regs.gpio_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (offset = 0; offset < PL061_GPIO_NR; offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (pl061->csave_regs.gpio_dir & (BIT(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pl061->csave_regs.gpio_data |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pl061_get_value(&pl061->gc, offset) << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int pl061_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct pl061 *pl061 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) for (offset = 0; offset < PL061_GPIO_NR; offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (pl061->csave_regs.gpio_dir & (BIT(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pl061_direction_output(&pl061->gc, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pl061->csave_regs.gpio_data &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (BIT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pl061_direction_input(&pl061->gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct dev_pm_ops pl061_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .suspend = pl061_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .resume = pl061_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .freeze = pl061_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .restore = pl061_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct amba_id pl061_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .id = 0x00041061,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_DEVICE_TABLE(amba, pl061_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct amba_driver pl061_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = "pl061_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .pm = &pl061_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .id_table = pl061_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .probe = pl061_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) module_amba_driver(pl061_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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