^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for the ACCES PCIe-IDIO-24 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License, version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This driver supports the following ACCES devices: PCIe-IDIO-24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Bit: Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 0: Enable Interrupt Sources (Bit 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 1: Enable Interrupt Sources (Bit 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 2: Generate Internal PCI Bus Internal SERR# Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 3: Mailbox Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 4: Power Management Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 5: Power Management Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 6: Slave Read Local Data Parity Check Error Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 7: Slave Read Local Data Parity Check Error Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 8: Internal PCI Wire Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 9: PCI Express Doorbell Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 10: PCI Abort Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 11: Local Interrupt Input Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 12: Retry Abort Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 13: PCI Express Doorbell Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 14: PCI Abort Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 15: Local Interrupt Input Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 16: Local Interrupt Output Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 17: Local Doorbell Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 18: DMA Channel 0 Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 19: DMA Channel 1 Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 20: Local Doorbell Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 21: DMA Channel 0 Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 22: DMA Channel 1 Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 23: Built-In Self-Test (BIST) Interrupt Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 24: Direct Master was the Bus Master during a Master or Target Abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 25: DMA Channel 0 was the Bus Master during a Master or Target Abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 26: DMA Channel 1 was the Bus Master during a Master or Target Abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 27: Target Abort after internal 256 consecutive Master Retrys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 28: PCI Bus wrote data to LCS_MBOX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 29: PCI Bus wrote data to LCS_MBOX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 30: PCI Bus wrote data to LCS_MBOX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 31: PCI Bus wrote data to LCS_MBOX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLX_PEX8311_PCI_LCS_INTCSR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define INTCSR_INTERNAL_PCI_WIRE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INTCSR_LOCAL_INPUT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * struct idio_24_gpio_reg - GPIO device registers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @out0_7: Read: FET Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Write: FET Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @out8_15: Read: FET Outputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Write: FET Outputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @out16_23: Read: FET Outputs 16-23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Write: FET Outputs 16-23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @ttl_out0_7: Read: TTL/CMOS Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Write: TTL/CMOS Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @in0_7: Read: Isolated Inputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Write: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @in8_15: Read: Isolated Inputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Write: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @in16_23: Read: Isolated Inputs 16-23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Write: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @ttl_in0_7: Read: TTL/CMOS Inputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Write: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @cos0_7: Read: COS Status Inputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Write: COS Clear Inputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @cos8_15: Read: COS Status Inputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Write: COS Clear Inputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @cos16_23: Read: COS Status Inputs 16-23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Write: COS Clear Inputs 16-23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Write: COS Clear TTL/CMOS 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @ctl: Read: Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Write: Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @reserved: Read: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Write: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @cos_enable: Read: COS Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Write: COS Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @soft_reset: Read: IRQ Output Pin Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Write: Software Board Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct idio_24_gpio_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 out8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 out16_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 ttl_out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 in0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 in8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 in16_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 ttl_in0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 cos0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 cos8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 cos16_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 cos_ttl0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 cos_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * struct idio_24_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @lock: synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @reg: I/O address offset for the GPIO device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @irq_mask: I/O bits affected by interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct idio_24_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u8 __iomem *plx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct idio_24_gpio_reg __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int idio_24_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* FET Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (offset < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Isolated Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (offset < 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* TTL/CMOS I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* OUT MODE = 1 when TTL/CMOS Output Mode is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int idio_24_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int ctl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* TTL/CMOS I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (offset > 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Clear TTL/CMOS Output Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) iowrite8(ctl_state, &idio24gpio->reg->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int idio_24_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int ctl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* TTL/CMOS I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (offset > 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Set TTL/CMOS Output Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iowrite8(ctl_state, &idio24gpio->reg->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) chip->set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const unsigned long offset_mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* FET Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (offset < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (offset < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Isolated Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (offset < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (offset < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (offset < 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* TTL/CMOS Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* TTL/CMOS Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) size_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* clear bits array to a clean slate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bitmap_zero(bits, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) index = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* read bits from current gpio port (port 6 is TTL GPIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (index < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) port_state = ioread8(ports[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) port_state &= gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) bitmap_set_value8(bits, port_state, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) const unsigned int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Isolated Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (offset > 23 && offset < 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* TTL/CMOS Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* TTL/CMOS Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (offset > 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) base = &idio24gpio->reg->ttl_out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* FET Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else if (offset > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) base = &idio24gpio->reg->out16_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else if (offset > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) base = &idio24gpio->reg->out8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) base = &idio24gpio->reg->out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) out_state = ioread8(base) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out_state = ioread8(base) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) iowrite8(out_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __iomem *ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) &idio24gpio->reg->out16_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) size_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const unsigned long out_mode_mask = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) index = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* read bits from current gpio port (port 6 is TTL GPIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (index < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) out_state = ioread8(ports[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* skip TTL GPIO if set for input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* set requested bit states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) out_state &= ~gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) out_state |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* write bits for current gpio port (port 6 is TTL GPIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (index < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) iowrite8(out_state, ports[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void idio_24_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void idio_24_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned char new_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) const unsigned long bank_offset = bit_offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned char cos_enable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) idio24gpio->irq_mask &= ~BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!new_irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Disable Rising Edge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cos_enable_state &= ~BIT(bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Disable Falling Edge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) cos_enable_state &= ~BIT(bank_offset + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void idio_24_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char prev_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const unsigned long bank_offset = bit_offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned char cos_enable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) raw_spin_lock_irqsave(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) idio24gpio->irq_mask |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!prev_irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Enable Rising Edge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cos_enable_state |= BIT(bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Enable Falling Edge detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cos_enable_state |= BIT(bank_offset + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int idio_24_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* The only valid irq types are none and both-edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (flow_type != IRQ_TYPE_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct irq_chip idio_24_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "pcie-idio-24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .irq_ack = idio_24_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .irq_mask = idio_24_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .irq_unmask = idio_24_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .irq_set_type = idio_24_irq_set_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static irqreturn_t idio_24_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct idio_24_gpio *const idio24gpio = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct gpio_chip *const chip = &idio24gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) raw_spin_lock(&idio24gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Read Change-Of-State status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) irq_status = ioread32(&idio24gpio->reg->cos0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) raw_spin_unlock(&idio24gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Make sure our device generated IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Handle only unmasked IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irq_mask = idio24gpio->irq_mask & irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) generic_handle_irq(irq_find_mapping(chip->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio + 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) raw_spin_lock(&idio24gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Clear Change-Of-State status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) iowrite32(irq_status, &idio24gpio->reg->cos0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) raw_spin_unlock(&idio24gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define IDIO_24_NGPIO 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char *idio_24_names[IDIO_24_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "OUT16", "OUT17", "OUT18", "OUT19", "OUT20", "OUT21", "OUT22", "OUT23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "IIN16", "IIN17", "IIN18", "IIN19", "IIN20", "IIN21", "IIN22", "IIN23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "TTL0", "TTL1", "TTL2", "TTL3", "TTL4", "TTL5", "TTL6", "TTL7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct device *const dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct idio_24_gpio *idio24gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const size_t pci_plx_bar_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) const size_t pci_bar_index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) const char *const name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!idio24gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(dev, "Failed to enable PCI device (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err = pcim_iomap_regions(pdev, BIT(pci_plx_bar_index) | BIT(pci_bar_index), name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) idio24gpio->chip.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) idio24gpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) idio24gpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) idio24gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) idio24gpio->chip.ngpio = IDIO_24_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) idio24gpio->chip.names = idio_24_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) idio24gpio->chip.get_direction = idio_24_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) idio24gpio->chip.direction_input = idio_24_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) idio24gpio->chip.direction_output = idio_24_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) idio24gpio->chip.get = idio_24_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) idio24gpio->chip.set = idio_24_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) girq = &idio24gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) girq->chip = &idio_24_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) raw_spin_lock_init(&idio24gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Software board reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) iowrite8(0, &idio24gpio->reg->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * enable PLX PEX8311 internal PCI wire interrupt and local interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) err = devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) name, idio24gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(dev, "IRQ handler registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct pci_device_id idio_24_pci_dev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { PCI_DEVICE(0x494F, 0x0FD0) }, { PCI_DEVICE(0x494F, 0x0BD0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { PCI_DEVICE(0x494F, 0x07D0) }, { PCI_DEVICE(0x494F, 0x0FC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MODULE_DEVICE_TABLE(pci, idio_24_pci_dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct pci_driver idio_24_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .name = "pcie-idio-24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .id_table = idio_24_pci_dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .probe = idio_24_probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) module_pci_driver(idio_24_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_DESCRIPTION("ACCES PCIe-IDIO-24 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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