^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for the ACCES PCI-IDIO-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * struct idio_16_gpio_reg - GPIO device registers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @out0_7: Read: FET Drive Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Write: FET Drive Outputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @in0_7: Read: Isolated Inputs 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Write: Clear Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @irq_ctl: Read: Enable IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Write: Disable IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @filter_ctl: Read: Activate Input Filters 0-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Write: Deactivate Input Filters 0-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @out8_15: Read: FET Drive Outputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Write: FET Drive Outputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @in8_15: Read: Isolated Inputs 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Write: Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @irq_status: Read: Interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Write: Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct idio_16_gpio_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 in0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 irq_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 filter_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 out8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 in8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct idio_16_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @lock: synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @reg: I/O address offset for the GPIO device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @irq_mask: I/O bits affected by interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct idio_16_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct idio_16_gpio_reg __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int idio_16_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (offset > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int idio_16_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int idio_16_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) chip->set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (offset < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return !!(ioread8(&idio16gpio->reg->out0_7) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return !!(ioread8(&idio16gpio->reg->out8_15) & (mask >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (offset < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return !!(ioread8(&idio16gpio->reg->in0_7) & (mask >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return !!(ioread8(&idio16gpio->reg->in8_15) & (mask >> 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) &idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &idio16gpio->reg->in0_7, &idio16gpio->reg->in8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* clear bits array to a clean slate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bitmap_zero(bits, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) port_addr = ports[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) port_state = ioread8(port_addr) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bitmap_set_value8(bits, port_state, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (offset > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (offset > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mask >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) base = &idio16gpio->reg->out8_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) base = &idio16gpio->reg->out0_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) out_state = ioread8(base) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_state = ioread8(base) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) iowrite8(out_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) size_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __iomem *port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) index = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) port_addr = ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out_state = ioread8(port_addr) & ~gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out_state |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iowrite8(out_state, port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void idio_16_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void idio_16_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const unsigned long mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) idio16gpio->irq_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!idio16gpio->irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) iowrite8(0, &idio16gpio->reg->irq_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void idio_16_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const unsigned long mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const unsigned long prev_irq_mask = idio16gpio->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) idio16gpio->irq_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!prev_irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ioread8(&idio16gpio->reg->irq_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* The only valid irq types are none and both-edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (flow_type != IRQ_TYPE_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct irq_chip idio_16_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "pci-idio-16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .irq_ack = idio_16_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .irq_mask = idio_16_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .irq_unmask = idio_16_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .irq_set_type = idio_16_irq_set_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct idio_16_gpio *const idio16gpio = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct gpio_chip *const chip = &idio16gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) raw_spin_lock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) irq_status = ioread8(&idio16gpio->reg->irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) raw_spin_unlock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Make sure our device generated IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!(irq_status & 0x3) || !(irq_status & 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) raw_spin_lock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iowrite8(0, &idio16gpio->reg->in0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) raw_spin_unlock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IDIO_16_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const char *idio_16_names[IDIO_16_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int idio_16_irq_init_hw(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Disable IRQ by default and clear any pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) iowrite8(0, &idio16gpio->reg->irq_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) iowrite8(0, &idio16gpio->reg->in0_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct device *const dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct idio_16_gpio *idio16gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const size_t pci_bar_index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) const char *const name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!idio16gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(dev, "Failed to enable PCI device (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Deactivate input filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) iowrite8(0, &idio16gpio->reg->filter_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) idio16gpio->chip.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) idio16gpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) idio16gpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) idio16gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) idio16gpio->chip.ngpio = IDIO_16_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) idio16gpio->chip.names = idio_16_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) idio16gpio->chip.get = idio_16_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) idio16gpio->chip.set = idio_16_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) girq = &idio16gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) girq->chip = &idio_16_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) girq->init_hw = idio_16_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) raw_spin_lock_init(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = devm_request_irq(dev, pdev->irq, idio_16_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) name, idio16gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_err(dev, "IRQ handler registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct pci_device_id idio_16_pci_dev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { PCI_DEVICE(0x494F, 0x0DC8) }, { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DEVICE_TABLE(pci, idio_16_pci_dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct pci_driver idio_16_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "pci-idio-16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .id_table = idio_16_pci_dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .probe = idio_16_probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) module_pci_driver(idio_16_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_DESCRIPTION("ACCES PCI-IDIO-16 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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