Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PCH_EDGE_FALLING	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PCH_EDGE_RISING		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PCH_LEVEL_L		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PCH_LEVEL_H		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PCH_EDGE_BOTH		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PCH_IM_MASK		GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PCH_IRQ_BASE		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct pch_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32	ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32	istatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32	idisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32	iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32	imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32	imaskclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32	po;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32	pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32	pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32	im0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32	im1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32	reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32	gpio_use_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32	reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) enum pch_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	INTEL_EG20T_PCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Specifies number of GPIO PINS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int gpio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[INTEL_EG20T_PCH] = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[OKISEMI_ML7223m_IOH] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[OKISEMI_ML7223n_IOH] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * struct pch_gpio_reg_data - The register store data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @ien_reg:	To store contents of IEN register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @imask_reg:	To store contents of IMASK register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @po_reg:	To store contents of PO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @pm_reg:	To store contents of PM register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @im0_reg:	To store contents of IM0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * @im1_reg:	To store contents of IM1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *		       (Only ML7223 Bus-n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct pch_gpio_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 ien_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 imask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 po_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 pm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 im0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 im1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 gpio_use_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * struct pch_gpio - GPIO private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @base:			PCI base address of Memory mapped I/O register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @reg:			Memory mapped PCH GPIO register list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * @dev:			Pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @gpio:			Data for GPIO infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @pch_gpio_reg:		Memory mapped Register data is saved here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *				when suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @lock:			Used for register access protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @irq_base:		Save base of IRQ number for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @ioh:		IOH ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * @spinlock:		Used for register access protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct pch_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct pch_regs __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct pch_gpio_reg_data pch_gpio_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	enum pch_type_t ioh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	spinlock_t spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	reg_val = ioread32(&chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		reg_val |= BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		reg_val &= ~BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	iowrite32(reg_val, &chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return !!(ioread32(&chip->reg->pi) & BIT(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				     int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	reg_val = ioread32(&chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		reg_val |= BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		reg_val &= ~BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	iowrite32(reg_val, &chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	pm = ioread32(&chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pm &= BIT(gpio_pins[chip->ioh]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	pm |= BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	iowrite32(pm, &chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pm = ioread32(&chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	pm &= BIT(gpio_pins[chip->ioh]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	pm &= ~BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	iowrite32(pm, &chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * Save register configuration and disable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (chip->ioh == INTEL_EG20T_PCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (chip->ioh == OKISEMI_ML7223n_IOH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * This function restores the register configuration of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* to store contents of PO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* to store contents of PM register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (chip->ioh == INTEL_EG20T_PCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (chip->ioh == OKISEMI_ML7223n_IOH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct pch_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return chip->irq_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void pch_gpio_setup(struct pch_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct gpio_chip *gpio = &chip->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	gpio->label = dev_name(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	gpio->parent = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	gpio->direction_input = pch_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	gpio->get = pch_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	gpio->direction_output = pch_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	gpio->set = pch_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	gpio->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	gpio->ngpio = gpio_pins[chip->ioh];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	gpio->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	gpio->to_irq = pch_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int pch_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct pch_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u32 im, im_pos, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u32 __iomem *im_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int ch, irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ch = irq - chip->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (irq < chip->irq_base + 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		im_reg = &chip->reg->im0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		im_pos = ch - 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		im_reg = &chip->reg->im1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		im_pos = ch - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		val = PCH_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		val = PCH_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		val = PCH_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		val = PCH_LEVEL_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		val = PCH_LEVEL_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* Set interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	iowrite32(im | (val << (im_pos * 4)), im_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* And the handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	else if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void pch_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct pch_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void pch_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct pch_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void pch_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct pch_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct pch_gpio *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	unsigned long reg_val = ioread32(&chip->reg->istatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		generic_handle_irq(chip->irq_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return IRQ_RETVAL(reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				       unsigned int irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				       unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					 chip->base, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	gc->private = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ct->chip.irq_ack = pch_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ct->chip.irq_mask = pch_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ct->chip.irq_unmask = pch_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ct->chip.irq_set_type = pch_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					 IRQ_GC_INIT_MASK_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 					 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int pch_gpio_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 				    const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct pch_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	chip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		dev_err(&pdev->dev, "pci_enable_device FAILED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	chip->base = pcim_iomap_table(pdev)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (pdev->device == 0x8803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		chip->ioh = INTEL_EG20T_PCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	else if (pdev->device == 0x8014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		chip->ioh = OKISEMI_ML7223m_IOH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	else if (pdev->device == 0x8043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		chip->ioh = OKISEMI_ML7223n_IOH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	chip->reg = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	pci_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	spin_lock_init(&chip->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	pch_gpio_setup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 					gpio_pins[chip->ioh], NUMA_NO_NODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		chip->irq_base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	chip->irq_base = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	/* Mask all interrupts, but enable them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			       IRQF_SHARED, KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		dev_err(&pdev->dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int __maybe_unused pch_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	struct pch_gpio *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	pch_gpio_save_reg_conf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int __maybe_unused pch_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	struct pch_gpio *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	iowrite32(0x01, &chip->reg->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	iowrite32(0x00, &chip->reg->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	pch_gpio_restore_reg_conf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct pci_device_id pch_gpio_pcidev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct pci_driver pch_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.name = "pch_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.id_table = pch_gpio_pcidev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.probe = pch_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.pm = &pch_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) module_pci_driver(pch_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_DESCRIPTION("PCH GPIO PCI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_LICENSE("GPL v2");