^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCA953x 4/8/16/24/40 bit I/O ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Derived from drivers/i2c/chips/pca9539.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/pca953x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCA953X_INPUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCA953X_OUTPUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCA953X_INVERT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCA953X_DIRECTION 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_ADDR_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_ADDR_EXT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_ADDR_AI BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCA957X_IN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCA957X_INVRT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCA957X_BKEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCA957X_PUPD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCA957X_CFG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCA957X_OUT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCA957X_MSK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCA957X_INTS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCAL953X_OUT_STRENGTH 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCAL953X_IN_LATCH 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCAL953X_PULL_EN 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCAL953X_PULL_SEL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCAL953X_INT_MASK 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCAL953X_INT_STAT 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCAL953X_OUT_CONF 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCAL6524_INT_EDGE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCAL6524_INT_CLR 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCAL6524_IN_STATUS 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCAL6524_OUT_INDCONF 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCAL6524_DEBOUNCE 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCA_GPIO_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCAL_GPIO_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCAL_PINCTRL_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCA_INT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCA_PCAL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCA953X_TYPE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCA957X_TYPE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCA_TYPE_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct i2c_device_id pca953x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "pca9536", 4 | PCA953X_TYPE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "pca9556", 8 | PCA953X_TYPE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "pca9557", 8 | PCA953X_TYPE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "pca9698", 40 | PCA953X_TYPE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "max7310", 8 | PCA953X_TYPE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "xra1202", 8 | PCA953X_TYPE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DEVICE_TABLE(i2c, pca953x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_GPIO_PCA953X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int pca953x_acpi_get_irq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_warn(dev, "can't add GPIO ACPI mapping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * On Intel Galileo Gen 2 board the IRQ pin of one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the I²C GPIO expanders, which has GpioInt() resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * is provided as an absolute number instead of being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * relative. Since first controller (gpio-sch.c) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * second (gpio-dwapb.c) are at the fixed bases, we may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * safely refer to the number in the global space to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * an IRQ out of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct acpi_device_id pca953x_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX_BANK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BANK_SZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAX_LINE (MAX_BANK * BANK_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pca953x_reg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct pca953x_reg_config pca953x_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .direction = PCA953X_DIRECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .output = PCA953X_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .input = PCA953X_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .invert = PCA953X_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct pca953x_reg_config pca957x_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .direction = PCA957X_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .output = PCA957X_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .input = PCA957X_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .invert = PCA957X_INVRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct pca953x_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned gpio_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mutex i2c_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_GPIO_PCA953X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DECLARE_BITMAP(irq_mask, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DECLARE_BITMAP(irq_stat, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) atomic_t wakeup_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const char *const *names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct pca953x_reg_config *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int pca953x_bank_shift(struct pca953x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PCA953x_BANK_INPUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PCA953x_BANK_OUTPUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PCA953x_BANK_POLARITY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PCA953x_BANK_CONFIG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCA957x_BANK_INPUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCA957x_BANK_POLARITY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PCA957x_BANK_BUSHOLD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PCA957x_BANK_CONFIG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PCA957x_BANK_OUTPUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * We care about the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * - Standard set, below 0x40, each port can be replicated up to 8 times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * - PCA953x standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Input port 0x00 + 0 * bank_size R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Output port 0x00 + 1 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Polarity Inversion port 0x00 + 2 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Configuration port 0x00 + 3 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * - PCA957x with mixed up registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Input port 0x00 + 0 * bank_size R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Polarity Inversion port 0x00 + 1 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Bus hold port 0x00 + 2 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Configuration port 0x00 + 4 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Output port 0x00 + 5 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * - Extended set, above 0x40, often chip specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Input latch register 0x40 + 2 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Interrupt mask register 0x40 + 5 * bank_size RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Interrupt status register 0x40 + 6 * bank_size R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * - Registers with bit 0x80 set, the AI bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * The bit is cleared and the registers fall into one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * categories above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 checkbank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int bank_shift = pca953x_bank_shift(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int bank = (reg & REG_ADDR_MASK) >> bank_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int offset = reg & (BIT(bank_shift) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Special PCAL extended register check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (reg & REG_ADDR_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!(chip->driver_data & PCA_PCAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bank += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Register is not in the matching bank. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!(BIT(bank) & checkbank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Register is not within allowed range of bank. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (offset >= NBANK(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static bool pca953x_readable_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PCA957x_BANK_BUSHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (chip->driver_data & PCA_PCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PCAL9xxx_BANK_IRQ_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return pca953x_check_register(chip, reg, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PCA953x_BANK_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (chip->driver_data & PCA_PCAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return pca953x_check_register(chip, reg, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bank = PCA953x_BANK_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bank = PCA957x_BANK_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (chip->driver_data & PCA_PCAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bank |= PCAL9xxx_BANK_IRQ_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return pca953x_check_register(chip, reg, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct regmap_config pca953x_i2c_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .readable_reg = pca953x_readable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .writeable_reg = pca953x_writeable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .volatile_reg = pca953x_volatile_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .disable_locking = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .max_register = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct regmap_config pca953x_ai_i2c_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .read_flag_mask = REG_ADDR_AI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .write_flag_mask = REG_ADDR_AI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .readable_reg = pca953x_readable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .writeable_reg = pca953x_writeable_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .volatile_reg = pca953x_volatile_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .disable_locking = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .max_register = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int bank_shift = pca953x_bank_shift(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 regaddr = pinctrl | addr | (off / BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 value[MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) for (i = 0; i < NBANK(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) value[i] = bitmap_get_value8(val, i * BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&chip->client->dev, "failed writing register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 value[MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&chip->client->dev, "failed reading register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (i = 0; i < NBANK(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bitmap_set_value8(val, value[i], i * BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 bit = BIT(off % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int pca953x_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned off, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 bit = BIT(off % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* set output level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* then direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 bit = BIT(off % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = regmap_read(chip->regmap, inreg, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return !!(reg_val & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 bit = BIT(off % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 bit = BIT(off % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = regmap_read(chip->regmap, dirreg, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (reg_val & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DECLARE_BITMAP(reg_val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DECLARE_BITMAP(reg_val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pca953x_write_regs(chip, chip->regs->output, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 bit = BIT(offset % BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * pull-up/pull-down configuration requires PCAL extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!(chip->driver_data & PCA_PCAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Configure pull-up/pull-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (config == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Disable/Enable pull-up/pull-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (config == PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return pca953x_gpio_set_pull_up_down(chip, offset, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) gc->direction_input = pca953x_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) gc->direction_output = pca953x_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) gc->get = pca953x_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) gc->set = pca953x_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) gc->get_direction = pca953x_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) gc->get_multiple = pca953x_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) gc->set_multiple = pca953x_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) gc->set_config = pca953x_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) gc->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) gc->base = chip->gpio_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) gc->ngpio = gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) gc->label = dev_name(&chip->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) gc->parent = &chip->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) gc->names = chip->names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifdef CONFIG_GPIO_PCA953X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void pca953x_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clear_bit(hwirq, chip->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void pca953x_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) set_bit(hwirq, chip->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) atomic_inc(&chip->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) atomic_dec(&chip->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return irq_set_irq_wake(chip->client->irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void pca953x_irq_bus_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mutex_lock(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) DECLARE_BITMAP(irq_mask, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) DECLARE_BITMAP(reg_direction, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (chip->driver_data & PCA_PCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Enable latch on interrupt-enabled inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Unmask enabled interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Switch direction to input if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pca953x_read_regs(chip, chip->regs->direction, reg_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bitmap_complement(reg_direction, reg_direction, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Look for any newly setup interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for_each_set_bit(level, irq_mask, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pca953x_gpio_direction_input(&chip->gpio_chip, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mutex_unlock(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!(type & IRQ_TYPE_EDGE_BOTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) d->irq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void pca953x_irq_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct pca953x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clear_bit(hwirq, chip->irq_trig_raise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) clear_bit(hwirq, chip->irq_trig_fall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct gpio_chip *gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) DECLARE_BITMAP(reg_direction, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) DECLARE_BITMAP(old_stat, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) DECLARE_BITMAP(cur_stat, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DECLARE_BITMAP(new_stat, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) DECLARE_BITMAP(trigger, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (chip->driver_data & PCA_PCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Read the current interrupt status from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Check latched inputs and clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Apply filter for rising/falling edge selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) bitmap_and(pending, new_stat, trigger, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return !bitmap_empty(pending, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Remove output pins from the equation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pca953x_read_regs(chip, chip->regs->direction, reg_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (bitmap_empty(trigger, gc->ngpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) bitmap_and(pending, new_stat, trigger, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return !bitmap_empty(pending, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static irqreturn_t pca953x_irq_handler(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct pca953x_chip *chip = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct gpio_chip *gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DECLARE_BITMAP(pending, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) bitmap_zero(pending, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_lock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = pca953x_irq_pending(chip, pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for_each_set_bit(level, pending, gc->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int nested_irq = irq_find_mapping(gc->irq.domain, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (unlikely(nested_irq <= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) handle_nested_irq(nested_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct irq_chip *irq_chip = &chip->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DECLARE_BITMAP(reg_direction, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DECLARE_BITMAP(irq_stat, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = pca953x_acpi_get_irq(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) client->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (irq_base == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!(chip->driver_data & PCA_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * There is no way to know which GPIO line generated the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * interrupt. We have to rely on the previous read for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * this purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pca953x_read_regs(chip, chip->regs->direction, reg_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mutex_init(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) irq_chip->name = dev_name(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) irq_chip->irq_mask = pca953x_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) irq_chip->irq_unmask = pca953x_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) irq_chip->irq_set_wake = pca953x_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) irq_chip->irq_set_type = pca953x_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) irq_chip->irq_shutdown = pca953x_irq_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) girq = &chip->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) girq->chip = irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) girq->first = irq_base; /* FIXME: get rid of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) NULL, pca953x_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_name(&client->dev), chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_err(&client->dev, "failed to request irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #else /* CONFIG_GPIO_PCA953X_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int pca953x_irq_setup(struct pca953x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_warn(&client->dev, "interrupt support not compiled in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DECLARE_BITMAP(val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = regcache_sync_region(chip->regmap, chip->regs->output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) chip->regs->output + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = regcache_sync_region(chip->regmap, chip->regs->direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) chip->regs->direction + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* set platform specific polarity inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) bitmap_fill(val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bitmap_zero(val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = pca953x_write_regs(chip, chip->regs->invert, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DECLARE_BITMAP(val, MAX_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = device_pca95xx_init(chip, invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* To enable register 6, 7 to control pull up and pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (i = 0; i < NBANK(chip); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) bitmap_set_value8(val, 0x02, i * BANK_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int pca953x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) const struct i2c_device_id *i2c_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct pca953x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct pca953x_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u32 invert = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) irq_base = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) chip->gpio_start = pdata->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) invert = pdata->invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) chip->names = pdata->names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) chip->gpio_start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * See if we need to de-assert a reset pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * There is no known ACPI-enabled platforms that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * using "reset" GPIO. Otherwise any of those platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * must use _DSD method with corresponding property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (IS_ERR(reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return PTR_ERR(reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) chip->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) reg = devm_regulator_get(&client->dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = regulator_enable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_err(&client->dev, "reg en err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) chip->regulator = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (i2c_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) chip->driver_data = i2c_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) const void *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) match = device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) chip->driver_data = (uintptr_t)match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) i2c_set_clientdata(client, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_info(&client->dev, "using AI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) regmap_config = &pca953x_ai_i2c_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dev_info(&client->dev, "using no AI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) regmap_config = &pca953x_i2c_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) chip->regmap = devm_regmap_init_i2c(client, regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (IS_ERR(chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = PTR_ERR(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) regcache_mark_dirty(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mutex_init(&chip->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * In case we have an i2c-mux controlled by a GPIO provided by an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * expander using the same driver higher on the device tree, read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * i2c adapter nesting depth and use the retrieved value as lockdep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * subclass for chip->i2c_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * REVISIT: This solution is not complete. It protects us from lockdep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * false positives when the expander controlling the i2c-mux is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * a different level on the device tree, but not when it's on the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * level on a different branch (in which case the subclass number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * would be the same).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * TODO: Once a correct solution is developed, a similar fix should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * applied to all other i2c-controlled GPIO expanders (and potentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * regmap-i2c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) lockdep_set_subclass(&chip->i2c_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) i2c_adapter_depth(client->adapter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* initialize cached registers from their original values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * we can't share this chip with another i2c master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) chip->regs = &pca953x_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = device_pca95xx_init(chip, invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) chip->regs = &pca957x_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = device_pca957x_init(chip, invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = pca953x_irq_setup(chip, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (pdata && pdata->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = pdata->setup(client, chip->gpio_chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) chip->gpio_chip.ngpio, pdata->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_warn(&client->dev, "setup failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) regulator_disable(chip->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int pca953x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct pca953x_chip *chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (pdata && pdata->teardown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = pdata->teardown(client, chip->gpio_chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) chip->gpio_chip.ngpio, pdata->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&client->dev, "teardown failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) regulator_disable(chip->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static int pca953x_regcache_sync(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * The ordering between direction and output is important,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * sync these registers first and only then sync the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = regcache_sync_region(chip->regmap, chip->regs->direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) chip->regs->direction + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = regcache_sync_region(chip->regmap, chip->regs->output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) chip->regs->output + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #ifdef CONFIG_GPIO_PCA953X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (chip->driver_data & PCA_PCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PCAL953X_IN_LATCH + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(dev, "Failed to sync INT latch registers: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PCAL953X_INT_MASK + NBANK(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_err(dev, "Failed to sync INT mask registers: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int pca953x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) regcache_cache_only(chip->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (atomic_read(&chip->wakeup_path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) device_set_wakeup_path(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) regulator_disable(chip->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int pca953x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct pca953x_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!atomic_read(&chip->wakeup_path)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = regulator_enable(chip->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(dev, "Failed to enable regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) regcache_cache_only(chip->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) regcache_mark_dirty(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = pca953x_regcache_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = regcache_sync(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_err(dev, "Failed to restore register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* convenience to stop overlong match-table lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const struct of_device_id pca953x_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static struct i2c_driver pca953x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .name = "pca953x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .pm = &pca953x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .of_match_table = pca953x_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .acpi_match_table = pca953x_acpi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .probe = pca953x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .remove = pca953x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .id_table = pca953x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int __init pca953x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return i2c_add_driver(&pca953x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* register after i2c postcore initcall and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * subsys initcalls that may rely on these GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) subsys_initcall(pca953x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static void __exit pca953x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) i2c_del_driver(&pca953x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) module_exit(pca953x_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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