^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support functions for OMAP GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written by Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/gpio-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 irqenable1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 irqenable2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 wake_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 leveldetect0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 leveldetect1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 risingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 fallingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 dataout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 debounce_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct omap_gpio_reg_offs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 enabled_non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_regs context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 saved_datain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 level_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 toggle_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) raw_spinlock_t wa_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk *dbck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int is_suspended:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int needs_resume:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 mod_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 irq_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 dbck_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool dbck_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool is_mpuio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool dbck_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bool loses_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bool context_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int context_loss_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int (*get_context_loss_count)(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPIO_MOD_CTRL_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LINE_USED(line, offset) (line & (BIT(offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void omap_gpio_unmask_irq(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 val = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int is_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BIT(gpio), is_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* set data out value using dedicate set/clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *reg = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 l = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg += bank->regs->set_dataout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bank->context.dataout |= l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg += bank->regs->clr_dataout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bank->context.dataout &= ~l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(l, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* set data out value using mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BIT(offset), enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (bank->dbck_enable_mask && !bank->dbck_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk_enable(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bank->dbck_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel_relaxed(bank->dbck_enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bank->base + bank->regs->debounce_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (bank->dbck_enable_mask && bank->dbck_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Disable debounce before cutting it's clock. If debounce is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * enabled but the clock is not, GPIO module seems to be unable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * to detect events and generate interrupts at least on OMAP3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writel_relaxed(0, bank->base + bank->regs->debounce_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_disable(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bank->dbck_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * omap2_set_gpio_debounce - low level gpio debounce time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @bank: the gpio bank we're acting upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @offset: the gpio number on this @bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @debounce: debounce time to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * OMAP's debounce time is in 31us steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * so we need to convert and round up to the closest unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Return: 0 on success, negative error otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool enable = !!debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!bank->dbck_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) debounce = DIV_ROUND_UP(debounce, 31) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) l = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clk_enable(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(debounce, bank->base + bank->regs->debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bank->dbck_enable_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_disable(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Enable debounce clock per module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * This call is mandatory because in omap_gpio_request() when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * *_runtime_get_sync() is called, _gpio_dbck_enable() within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * runtime callbck fails to turn on dbck because dbck_enable_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * used within _gpio_dbck_enable() is still not initialized at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * that point. Therefore we have to enable dbck here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) omap_gpio_dbck_enable(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (bank->dbck_enable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bank->context.debounce = debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bank->context.debounce_en = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * omap_clear_gpio_debounce - clear debounce settings for a gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @bank: the gpio bank we're acting upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @offset: the gpio number on this @bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * If a gpio is using debounce, then clear the debounce enable bit and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * this is the only gpio in this bank using debounce, then clear the debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * time too. The debounce clock will also be disabled when calling this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * if this is the only gpio in the bank using debounce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 gpio_bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!bank->dbck_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!(bank->dbck_enable_mask & gpio_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bank->dbck_enable_mask &= ~gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bank->context.debounce_en &= ~gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel_relaxed(bank->context.debounce_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bank->base + bank->regs->debounce_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!bank->dbck_enable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bank->context.debounce = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel_relaxed(bank->context.debounce, bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bank->regs->debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clk_disable(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bank->dbck_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * are capable waking up the system from off mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 no_wake = bank->non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (no_wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return !!(~no_wake & gpio_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void __iomem *base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 gpio_bit = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) trigger & IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) trigger & IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * We need the edge detection enabled for to allow the GPIO block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * to be woken from idle state. Set the appropriate edge detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * in addition to the level detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bank->context.leveldetect0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) readl_relaxed(bank->base + bank->regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bank->context.leveldetect1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) readl_relaxed(bank->base + bank->regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bank->context.risingdetect =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) readl_relaxed(bank->base + bank->regs->risingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bank->context.fallingdetect =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) readl_relaxed(bank->base + bank->regs->fallingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bank->level_mask = bank->context.leveldetect0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bank->context.leveldetect1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* This part needs to be executed always for OMAP{34xx, 44xx} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Log the edge gpio and manually trigger the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * after resume if the input level changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * to avoid irq lost during PER RET/OFF mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Applies for omap2 non-wakeup gpio and all omap3 gpios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (trigger & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bank->enabled_non_wakeup_gpios |= gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) bank->enabled_non_wakeup_gpios &= ~gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * This only applies to chips that can't do both rising and falling edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * detection at once. For all other chips, this function is a noop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __iomem *reg = bank->base + bank->regs->irqctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void __iomem *reg = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) omap_set_gpio_trigger(bank, gpio, trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } else if (bank->regs->irqctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg += bank->regs->irqctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) l = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bank->toggle_mask |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (trigger & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) l |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else if (trigger & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) l &= ~(BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel_relaxed(l, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else if (bank->regs->edgectrl1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (gpio & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg += bank->regs->edgectrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reg += bank->regs->edgectrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) gpio &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) l = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) l &= ~(3 << (gpio << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (trigger & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) l |= 2 << (gpio << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (trigger & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) l |= BIT(gpio << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel_relaxed(l, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (bank->regs->pinctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void __iomem *reg = bank->base + bank->regs->pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Claim the pin for MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (bank->regs->ctrl && !BANK_USED(bank)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void __iomem *reg = bank->base + bank->regs->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctrl = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Module is enabled, clocks are not gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ctrl &= ~GPIO_MOD_CTRL_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel_relaxed(ctrl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) bank->context.ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (bank->regs->ctrl && !BANK_USED(bank)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void __iomem *reg = bank->base + bank->regs->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ctrl = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Module is disabled, clocks are gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ctrl |= GPIO_MOD_CTRL_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel_relaxed(ctrl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) bank->context.ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void __iomem *reg = bank->base + bank->regs->direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return readl_relaxed(reg) & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!LINE_USED(bank->mod_usage, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) omap_enable_gpio_module(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) omap_set_gpio_direction(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bank->irq_usage |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (type & ~IRQ_TYPE_SENSE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!bank->regs->leveldetect0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) retval = omap_set_gpio_triggering(bank, offset, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) omap_gpio_init_irq(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!omap_gpio_is_input(bank, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Edge IRQs are already cleared/acked in irq_handler and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * not need to be masked, as result handle_edge_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * logic is excessed here and may cause lose of interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * So just use handle_simple_irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) irq_set_handler_locked(d, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void __iomem *reg = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reg += bank->regs->irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel_relaxed(gpio_mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Workaround for clearing DSP GPIO interrupts to allow retention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (bank->regs->irqstatus2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reg = bank->base + bank->regs->irqstatus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel_relaxed(gpio_mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Flush posted write for the irq status to avoid spurious interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) omap_clear_gpio_irqbank(bank, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void __iomem *reg = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 mask = (BIT(bank->width)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reg += bank->regs->irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) l = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (bank->regs->irqenable_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) l = ~l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) l &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned offset, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void __iomem *reg = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 gpio_mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) reg += bank->regs->set_irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bank->context.irqenable1 |= gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) reg += bank->regs->clr_irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bank->context.irqenable1 &= ~gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writel_relaxed(gpio_mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bank->context.irqenable1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) enable ^ bank->regs->irqenable_inv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * note requiring correlation between the IRQ enable registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * the wakeup registers. In any case, we want wakeup from idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * enabled for the GPIOs which support this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (bank->regs->wkup_en &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bank->context.wake_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) omap_gpio_rmw(bank->base + bank->regs->wkup_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gpio_mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return irq_set_irq_wake(bank->irq, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * We need to unmask the GPIO bank interrupt as soon as possible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * avoid missing GPIO interrupts for other lines in the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Then we need to mask-read-clear-unmask the triggered GPIO lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * in the bank to avoid missing nested interrupts for a GPIO line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * If we wait to unmask individual GPIO lines in the bank after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * line's interrupt handler has been run, we may miss some nested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void __iomem *isr_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 enabled, isr, edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct gpio_bank *bank = gpiobank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long wa_lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) isr_reg = bank->base + bank->regs->irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (WARN_ON(!isr_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "gpio irq%i while runtime suspended?\n", irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) raw_spin_lock_irqsave(&bank->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enabled = omap_get_gpio_irqbank_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) isr = readl_relaxed(isr_reg) & enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Clear edge sensitive interrupts before calling handler(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * so subsequent edge transitions are not missed while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * handlers are running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) edge = isr & ~bank->level_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) omap_clear_gpio_irqbank(bank, edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) while (isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bit = __ffs(isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) isr &= ~(BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) raw_spin_lock_irqsave(&bank->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Some chips can't respond to both rising and falling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * at the same time. If this irq was requested with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * both flags, we need to flip the ICR data for the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * to respond to the IRQ for the opposite direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * This will be indicated in the bank toggle_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (bank->toggle_mask & (BIT(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) omap_toggle_gpio_edge_triggering(bank, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) raw_spin_unlock_irqrestore(&bank->wa_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) wa_lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static unsigned int omap_gpio_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!LINE_USED(bank->mod_usage, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) omap_set_gpio_direction(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) omap_enable_gpio_module(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bank->irq_usage |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) omap_gpio_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void omap_gpio_irq_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bank->irq_usage &= ~(BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) omap_clear_gpio_irqstatus(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) omap_set_gpio_irqenable(bank, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!LINE_USED(bank->mod_usage, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) omap_clear_gpio_debounce(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) omap_disable_gpio_module(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void omap_gpio_irq_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct gpio_bank *bank = omap_irq_data_get_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pm_runtime_get_sync(bank->chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void gpio_irq_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct gpio_bank *bank = omap_irq_data_get_bank(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pm_runtime_put(bank->chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void omap_gpio_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) omap_set_gpio_irqenable(bank, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void omap_gpio_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct gpio_bank *bank = omap_irq_data_get_bank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 trigger = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) omap_set_gpio_irqenable(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * For level-triggered GPIOs, clearing must be done after the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * is cleared, thus after the handler has run. OMAP4 needs this done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * after enabing the interrupt to clear the wakeup status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) omap_clear_gpio_irqstatus(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) omap_set_gpio_triggering(bank, offset, trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int omap_mpuio_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) void __iomem *mask_reg = bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) OMAP_MPUIO_GPIO_MASKIT / bank->stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int omap_mpuio_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) void __iomem *mask_reg = bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) OMAP_MPUIO_GPIO_MASKIT / bank->stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) writel_relaxed(bank->context.wake_en, mask_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .suspend_noirq = omap_mpuio_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .resume_noirq = omap_mpuio_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* use platform_driver for this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static struct platform_driver omap_mpuio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .name = "mpuio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .pm = &omap_mpuio_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct platform_device omap_mpuio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "mpuio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .driver = &omap_mpuio_driver.driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* could list the /proc/iomem resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static inline void omap_mpuio_init(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) platform_set_drvdata(&omap_mpuio_device, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (platform_driver_register(&omap_mpuio_driver) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (void) platform_device_register(&omap_mpuio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pm_runtime_get_sync(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) omap_enable_gpio_module(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) bank->mod_usage |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) bank->mod_usage &= ~(BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!LINE_USED(bank->irq_usage, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) omap_set_gpio_direction(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) omap_clear_gpio_debounce(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) omap_disable_gpio_module(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_put(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) omap_set_gpio_direction(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (omap_gpio_is_input(bank, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) reg = bank->base + bank->regs->datain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) reg = bank->base + bank->regs->dataout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return (readl_relaxed(reg) & BIT(offset)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) bank->set_dataout(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) omap_set_gpio_direction(bank, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) void __iomem *base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 direction, m, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) direction = readl_relaxed(base + bank->regs->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) m = direction & *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) val |= readl_relaxed(base + bank->regs->datain) & m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) m = ~direction & *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) val |= readl_relaxed(base + bank->regs->dataout) & m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) *bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = omap2_set_gpio_debounce(bank, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_info(chip->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "Could not set line %u debounce to %u microseconds (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) offset, debounce, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = gpiochip_generic_config(chip, offset, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = omap_gpio_debounce(chip, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) bank->set_dataout(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) void __iomem *reg = bank->base + bank->regs->dataout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) writel_relaxed(l, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) bank->context.dataout = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static void omap_gpio_show_rev(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static bool called;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (called || bank->regs->revision == USHRT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rev = readw_relaxed(bank->base + bank->regs->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pr_info("OMAP GPIO hardware version %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) (rev >> 4) & 0x0f, rev & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) called = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static void omap_gpio_mod_init(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) void __iomem *base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 l = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (bank->width == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) l = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (bank->is_mpuio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) writel_relaxed(l, bank->base + bank->regs->irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) omap_gpio_rmw(base + bank->regs->irqenable, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) bank->regs->irqenable_inv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) omap_gpio_rmw(base + bank->regs->irqstatus, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) !bank->regs->irqenable_inv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (bank->regs->debounce_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) writel_relaxed(0, base + bank->regs->debounce_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Save OE default value (0xffffffff) in the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Initialize interface clk ungated, module enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (bank->regs->ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) writel_relaxed(0, base + bank->regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * REVISIT eventually switch from OMAP-specific gpio structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * over to the generic ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bank->chip.request = omap_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bank->chip.free = omap_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) bank->chip.get_direction = omap_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) bank->chip.direction_input = omap_gpio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) bank->chip.get = omap_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) bank->chip.get_multiple = omap_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) bank->chip.direction_output = omap_gpio_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) bank->chip.set_config = omap_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) bank->chip.set = omap_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) bank->chip.set_multiple = omap_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (bank->is_mpuio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) bank->chip.label = "mpuio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (bank->regs->wkup_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) bank->chip.parent = &omap_mpuio_device.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) bank->chip.base = OMAP_MPUIO(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) gpio, gpio + bank->width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bank->chip.label = label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bank->chip.base = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) bank->chip.ngpio = bank->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef CONFIG_ARCH_OMAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * irq_alloc_descs() since a base IRQ offset will no longer be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) irq_base = devm_irq_alloc_descs(bank->chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) -1, 0, bank->width, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* MPUIO is a bit different, reading IRQ status clears it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (bank->is_mpuio && !bank->regs->wkup_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) irqc->irq_set_wake = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) irq = &bank->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) irq->chip = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) irq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) irq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) irq->parents = &bank->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) irq->first = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = gpiochip_add_data(&bank->chip, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_err(bank->chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) "Could not register gpio chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = devm_request_irq(bank->chip.parent, bank->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) omap_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) 0, dev_name(bank->chip.parent), bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) gpiochip_remove(&bank->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (!bank->is_mpuio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) gpio += bank->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static void omap_gpio_init_context(struct gpio_bank *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) const struct omap_gpio_reg_offs *regs = p->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) void __iomem *base = p->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) p->context.ctrl = readl_relaxed(base + regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) p->context.oe = readl_relaxed(base + regs->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) p->context.wake_en = readl_relaxed(base + regs->wkup_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) p->context.dataout = readl_relaxed(base + regs->dataout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) p->context_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void omap_gpio_restore_context(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) const struct omap_gpio_reg_offs *regs = bank->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) void __iomem *base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writel_relaxed(bank->context.ctrl, base + regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) writel_relaxed(bank->context.dataout, base + regs->dataout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) writel_relaxed(bank->context.oe, base + regs->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (bank->dbck_enable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) writel_relaxed(bank->context.debounce, base + regs->debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) writel_relaxed(bank->context.debounce_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) base + regs->debounce_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct device *dev = bank->chip.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) void __iomem *base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u32 mask, nowake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) bank->saved_datain = readl_relaxed(base + bank->regs->datain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Save syconfig, it's runtime value can be different from init value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (bank->loses_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!bank->enabled_non_wakeup_gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) goto update_gpio_context_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mask &= ~bank->context.risingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) bank->saved_datain |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mask &= ~bank->context.fallingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) bank->saved_datain &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!may_lose_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) goto update_gpio_context_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * If going to OFF, remove triggering for all wkup domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * non-wakeup GPIOs. Otherwise spurious IRQs will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * generated. See OMAP2420 Errata item 1.101.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) nowake = bank->enabled_non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) update_gpio_context_count:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (bank->get_context_loss_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) bank->context_loss_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) bank->get_context_loss_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) omap_gpio_dbck_disable(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static void omap_gpio_unidle(struct gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct device *dev = bank->chip.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) u32 l = 0, gen, gen0, gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * On the first resume during the probe, the context has not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * been initialised and so initialise it now. Also initialise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * the context loss count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (bank->loses_context && !bank->context_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) omap_gpio_init_context(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (bank->get_context_loss_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) bank->context_loss_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) bank->get_context_loss_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) omap_gpio_dbck_enable(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (bank->loses_context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!bank->get_context_loss_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) omap_gpio_restore_context(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) c = bank->get_context_loss_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (c != bank->context_loss_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) omap_gpio_restore_context(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Restore changes done for OMAP2420 errata 1.101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) writel_relaxed(bank->context.fallingdetect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) bank->base + bank->regs->fallingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) writel_relaxed(bank->context.risingdetect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) bank->base + bank->regs->risingdetect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) l = readl_relaxed(bank->base + bank->regs->datain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * Check if any of the non-wakeup interrupt GPIOs have changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * state. If so, generate an IRQ by software. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * horribly racy, but it's the best we can do to work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * this silicon bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) l ^= bank->saved_datain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) l &= bank->enabled_non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * No need to generate IRQs for the rising edge for gpio IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * configured with falling edge only; and vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) gen0 = l & bank->context.fallingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) gen0 &= bank->saved_datain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) gen1 = l & bank->context.risingdetect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) gen1 &= ~(bank->saved_datain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* FIXME: Consider GPIO IRQs with level detections properly! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) gen = l & (~(bank->context.fallingdetect) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ~(bank->context.risingdetect));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Consider all GPIO IRQs needed to be updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) gen |= gen0 | gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (gen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u32 old0, old1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (!bank->regs->irqstatus_raw0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) writel_relaxed(old0 | gen, bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) bank->regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) writel_relaxed(old1 | gen, bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) bank->regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (bank->regs->irqstatus_raw0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) writel_relaxed(old0 | l, bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bank->regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) writel_relaxed(old1 | l, bank->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) bank->regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int gpio_omap_cpu_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) int ret = NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u32 isr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) bank = container_of(nb, struct gpio_bank, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (bank->is_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mask = omap_get_gpio_irqbank_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) omap_gpio_idle(bank, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) omap_gpio_unidle(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const struct omap_gpio_reg_offs omap2_gpio_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .revision = OMAP24XX_GPIO_REVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .sysconfig = OMAP24XX_GPIO_SYSCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .direction = OMAP24XX_GPIO_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .datain = OMAP24XX_GPIO_DATAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .dataout = OMAP24XX_GPIO_DATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .irqenable = OMAP24XX_GPIO_IRQENABLE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .ctrl = OMAP24XX_GPIO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .wkup_en = OMAP24XX_GPIO_WAKE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const struct omap_gpio_reg_offs omap4_gpio_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .revision = OMAP4_GPIO_REVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .sysconfig = OMAP4_GPIO_SYSCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .direction = OMAP4_GPIO_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .datain = OMAP4_GPIO_DATAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .dataout = OMAP4_GPIO_DATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .set_dataout = OMAP4_GPIO_SETDATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .irqstatus = OMAP4_GPIO_IRQSTATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .ctrl = OMAP4_GPIO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .wkup_en = OMAP4_GPIO_IRQWAKEN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .risingdetect = OMAP4_GPIO_RISINGDETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const struct omap_gpio_platform_data omap2_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .regs = &omap2_gpio_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .bank_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .dbck_flag = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static const struct omap_gpio_platform_data omap3_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .regs = &omap2_gpio_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .bank_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .dbck_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const struct omap_gpio_platform_data omap4_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .regs = &omap4_gpio_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .bank_width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .dbck_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const struct of_device_id omap_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .compatible = "ti,omap4-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .data = &omap4_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .compatible = "ti,omap3-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .data = &omap3_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .compatible = "ti,omap2-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .data = &omap2_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) MODULE_DEVICE_TABLE(of, omap_gpio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int omap_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) const struct omap_gpio_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) match = of_match_device(of_match_ptr(omap_gpio_match), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pdata = match ? match->data : dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (!irqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) irqc->irq_startup = omap_gpio_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) irqc->irq_shutdown = omap_gpio_irq_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) irqc->irq_ack = dummy_irq_chip.irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) irqc->irq_mask = omap_gpio_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) irqc->irq_unmask = omap_gpio_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) irqc->irq_set_type = omap_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) irqc->irq_set_wake = omap_gpio_wake_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) irqc->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) irqc->parent_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) bank->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (bank->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (!bank->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) bank->irq = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) bank->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) bank->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) bank->dbck_flag = pdata->dbck_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) bank->stride = pdata->bank_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) bank->width = pdata->bank_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) bank->is_mpuio = pdata->is_mpuio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) bank->regs = pdata->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) bank->chip.of_node = of_node_get(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (!of_property_read_bool(node, "ti,gpio-always-on"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) bank->loses_context = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) bank->loses_context = pdata->loses_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (bank->loses_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) bank->get_context_loss_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) pdata->get_context_loss_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (bank->regs->set_dataout && bank->regs->clr_dataout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) bank->set_dataout = omap_set_gpio_dataout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) bank->set_dataout = omap_set_gpio_dataout_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) raw_spin_lock_init(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) raw_spin_lock_init(&bank->wa_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Static mapping, never released */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) bank->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (IS_ERR(bank->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return PTR_ERR(bank->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (bank->dbck_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) bank->dbck = devm_clk_get(dev, "dbclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (IS_ERR(bank->dbck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) "Could not get gpio dbck. Disable debounce\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) bank->dbck_flag = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) clk_prepare(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) platform_set_drvdata(pdev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (bank->is_mpuio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) omap_mpuio_init(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) omap_gpio_mod_init(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = omap_gpio_chip_init(bank, irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (bank->dbck_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) clk_unprepare(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) omap_gpio_show_rev(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) bank->nb.notifier_call = gpio_omap_cpu_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) cpu_pm_register_notifier(&bank->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static int omap_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) struct gpio_bank *bank = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) cpu_pm_unregister_notifier(&bank->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) gpiochip_remove(&bank->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (bank->dbck_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) clk_unprepare(bank->dbck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) omap_gpio_idle(bank, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) bank->is_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) raw_spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) omap_gpio_unidle(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) bank->is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) raw_spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static int __maybe_unused omap_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (bank->is_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) bank->needs_resume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return omap_gpio_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static int __maybe_unused omap_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct gpio_bank *bank = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!bank->needs_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) bank->needs_resume = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return omap_gpio_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static const struct dev_pm_ops gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static struct platform_driver omap_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .probe = omap_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .remove = omap_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .name = "omap_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .pm = &gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .of_match_table = omap_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * gpio driver register needs to be done before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * machine_init functions access gpio APIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * Hence omap_gpio_drv_reg() is a postcore_initcall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static int __init omap_gpio_drv_reg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return platform_driver_register(&omap_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) postcore_initcall(omap_gpio_drv_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static void __exit omap_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) platform_driver_unregister(&omap_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) module_exit(omap_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) MODULE_DESCRIPTION("omap gpio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MODULE_ALIAS("platform:gpio-omap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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