Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Based on code from Freescale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MXS_SET		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MXS_CLR		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPIO_INT_FALL_EDGE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GPIO_INT_LOW_LEV	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GPIO_INT_RISE_EDGE	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GPIO_INT_HIGH_LEV	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GPIO_INT_LEV_MASK	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GPIO_INT_POL_MASK	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum mxs_gpio_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	IMX23_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	IMX28_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct mxs_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	enum mxs_gpio_id devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 both_edges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline int is_imx23_gpio(struct mxs_gpio_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return port->devid == IMX23_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static inline int is_imx28_gpio(struct mxs_gpio_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return port->devid == IMX28_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Note: This driver assumes 32 GPIOs are handled in one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 pin_mask = 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct mxs_gpio_port *port = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	void __iomem *pin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (!(ct->type & type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (irq_setup_alt_chip(d, type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	port->both_edges &= ~pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			edge = GPIO_INT_FALL_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			edge = GPIO_INT_RISE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		port->both_edges |= pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		edge = GPIO_INT_RISE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		edge = GPIO_INT_FALL_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		edge = GPIO_INT_LOW_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		edge = GPIO_INT_HIGH_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* set level or edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	pin_addr = port->base + PINCTRL_IRQLEV(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (edge & GPIO_INT_LEV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		writel(pin_mask, pin_addr + MXS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		writel(pin_mask, pin_addr + MXS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* set polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	pin_addr = port->base + PINCTRL_IRQPOL(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (edge & GPIO_INT_POL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		writel(pin_mask, pin_addr + MXS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		writel(pin_mask, pin_addr + MXS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 bit, val, edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	void __iomem *pin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	bit = 1 << gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	pin_addr = port->base + PINCTRL_IRQPOL(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	val = readl(pin_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	edge = val & bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		writel(bit, pin_addr + MXS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		writel(bit, pin_addr + MXS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* MXS has one interrupt *per* gpio port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void mxs_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			readl(port->base + PINCTRL_IRQEN(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	while (irq_stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		int irqoffset = fls(irq_stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		if (port->both_edges & (1 << irqoffset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			mxs_flip_edge(port, irqoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		irq_stat &= ~(1 << irqoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * Set interrupt number "irq" in the GPIO as a wake-up source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * While system is running, all registered GPIO interrupts need to have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * wake-up enabled. When system is suspended, only selected GPIO interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * need to have wake-up enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * @param  irq          interrupt source number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * @param  enable       enable as wake-up if equal to non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * @return       This function returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct mxs_gpio_port *port = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		enable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		disable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 					 port->base, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	gc->private = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ct = &gc->chip_types[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ct->chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ct = &gc->chip_types[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ct->chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ct->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					 IRQ_GC_INIT_NESTED_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					 IRQ_NOREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct mxs_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return irq_find_mapping(port->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct mxs_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u32 mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	dir = readl(port->base + PINCTRL_DOE(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (dir & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct platform_device_id mxs_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.name = "imx23-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.driver_data = IMX23_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.name = "imx28-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.driver_data = IMX28_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id mxs_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int mxs_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct mxs_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	port->id = of_alias_get_id(np, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (port->id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return port->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	port->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (port->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * map memory region only once, as all the gpio ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 * share the same one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		parent = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		base = of_iomap(parent, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	port->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* initially disable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	writel(0, port->base + PINCTRL_PIN2IRQ(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	writel(0, port->base + PINCTRL_IRQEN(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	/* clear address has to be used to clear IRQSTAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		err = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					     &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!port->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* gpio-mxs can be a generic irq chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	err = mxs_gpio_init_gc(port, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		goto out_irqdomain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* setup one handler for each entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 					 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	err = bgpio_init(&port->gc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			 port->base + PINCTRL_DIN(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			 port->base + PINCTRL_DOUT(port) + MXS_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			 port->base + PINCTRL_DOE(port), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		goto out_irqdomain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	port->gc.to_irq = mxs_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	port->gc.get_direction = mxs_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	port->gc.base = port->id * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	err = gpiochip_add_data(&port->gc, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		goto out_irqdomain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) out_irqdomain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	irq_domain_remove(port->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	iounmap(port->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct platform_driver mxs_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.name	= "gpio-mxs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.of_match_table = mxs_gpio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.probe		= mxs_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.id_table	= mxs_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int __init mxs_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return platform_driver_register(&mxs_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) postcore_initcall(mxs_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_AUTHOR("Freescale Semiconductor, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	      "Daniel Mack <danielncaiaq.de>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	      "Juergen Beisert <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_DESCRIPTION("Freescale MXS GPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_LICENSE("GPL");