^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Based on code from Freescale Semiconductor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Authors: Daniel Mack, Juergen Beisert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum mxc_gpio_hwtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) IMX1_GPIO, /* runs on i.mx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) IMX31_GPIO, /* runs on i.mx31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) IMX35_GPIO, /* runs on all other i.mx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* device type dependent stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mxc_gpio_hwdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned dr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned gdir_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned psr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned icr1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned icr2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned imr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned isr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int edge_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned low_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned high_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned rise_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned fall_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mxc_gpio_reg_saved {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 icr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 icr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 gdir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 edge_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mxc_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 both_edges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct mxc_gpio_reg_saved gpio_saved_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .dr_reg = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .gdir_reg = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .psr_reg = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .icr1_reg = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .icr2_reg = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .imr_reg = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .isr_reg = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .edge_sel_reg = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .low_level = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .high_level = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .rise_edge = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .fall_edge = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .dr_reg = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .gdir_reg = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .psr_reg = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .icr1_reg = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .icr2_reg = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .imr_reg = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .isr_reg = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .edge_sel_reg = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .low_level = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .high_level = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .rise_edge = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .fall_edge = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .dr_reg = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .gdir_reg = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .psr_reg = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .icr1_reg = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .icr2_reg = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .imr_reg = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .isr_reg = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .edge_sel_reg = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .low_level = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .high_level = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .rise_edge = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .fall_edge = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static enum mxc_gpio_hwtype mxc_gpio_hwtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPIO_INT_BOTH_EDGES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct platform_device_id mxc_gpio_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "imx1-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .driver_data = IMX1_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "imx21-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .driver_data = IMX21_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "imx31-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .driver_data = IMX31_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "imx35-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .driver_data = IMX35_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct of_device_id mxc_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * MX2 has one interrupt *for all* gpio ports. The list is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * to save the references to all ports, so that mx2_gpio_irq_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * can walk through all interrupt status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static LIST_HEAD(mxc_gpio_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Note: This driver assumes 32 GPIOs are handled in one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int gpio_set_irq_type(struct irq_data *d, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mxc_gpio_port *port = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 bit, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 gpio_idx = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __iomem *reg = port->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) port->both_edges &= ~(1 << gpio_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) edge = GPIO_INT_RISE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) edge = GPIO_INT_FALL_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (GPIO_EDGE_SEL >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) edge = GPIO_INT_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = port->gc.get(&port->gc, gpio_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) edge = GPIO_INT_LOW_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) edge = GPIO_INT_HIGH_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) port->both_edges |= 1 << gpio_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) edge = GPIO_INT_LOW_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) edge = GPIO_INT_HIGH_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (GPIO_EDGE_SEL >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val = readl(port->base + GPIO_EDGE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (edge == GPIO_INT_BOTH_EDGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(val | (1 << gpio_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) port->base + GPIO_EDGE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(val & ~(1 << gpio_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) port->base + GPIO_EDGE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (edge != GPIO_INT_BOTH_EDGES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bit = gpio_idx & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = readl(reg) & ~(0x3 << (bit << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(val | (edge << (bit << 1)), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(1 << gpio_idx, port->base + GPIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void __iomem *reg = port->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 bit, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bit = gpio & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) edge = (val >> (bit << 1)) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val &= ~(0x3 << (bit << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (edge == GPIO_INT_HIGH_LEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) edge = GPIO_INT_LOW_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else if (edge == GPIO_INT_LOW_LEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) edge = GPIO_INT_HIGH_LEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_err("mxc: invalid configuration for GPIO %d: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gpio, edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(val | (edge << (bit << 1)), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* handle 32 interrupts in one status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (irq_stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int irqoffset = fls(irq_stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (port->both_edges & (1 << irqoffset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mxc_flip_edge(port, irqoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) irq_stat &= ~(1 << irqoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* MX1 and MX3 has one interrupt *per* gpio port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void mx3_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mxc_gpio_irq_handler(port, irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* MX2 has one interrupt *for all* gpio ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void mx2_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 irq_msk, irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct mxc_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* walk through all interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) list_for_each_entry(port, &mxc_gpio_ports, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) irq_msk = readl(port->base + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!irq_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (irq_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mxc_gpio_irq_handler(port, irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Set interrupt number "irq" in the GPIO as a wake-up source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * While system is running, all registered GPIO interrupts need to have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * wake-up enabled. When system is suspended, only selected GPIO interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * need to have wake-up enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @param irq interrupt source number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @param enable enable as wake-up if equal to non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @return This function returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct mxc_gpio_port *port = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 gpio_idx = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (port->irq_high && (gpio_idx >= 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = enable_irq_wake(port->irq_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = enable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (port->irq_high && (gpio_idx >= 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = disable_irq_wake(port->irq_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = disable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) port->base, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) gc->private = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ct->chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ct->chip.irq_set_type = gpio_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ct->chip.irq_set_wake = gpio_set_wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ct->regs.ack = GPIO_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ct->regs.mask = GPIO_IMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) IRQ_GC_INIT_NESTED_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) IRQ_NOREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void mxc_gpio_get_hw(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) of_match_device(mxc_gpio_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enum mxc_gpio_hwtype hwtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pdev->id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hwtype = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (mxc_gpio_hwtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * The driver works with a reasonable presupposition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * that is all gpio ports must be the same type when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * running on one soc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BUG_ON(mxc_gpio_hwtype != hwtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (hwtype == IMX35_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mxc_gpio_hwdata = &imx35_gpio_hwdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else if (hwtype == IMX31_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mxc_gpio_hwdata = &imx31_gpio_hwdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mxc_gpio_hwtype = hwtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct mxc_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return irq_find_mapping(port->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int mxc_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct mxc_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mxc_gpio_get_hw(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) port->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (IS_ERR(port->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return PTR_ERR(port->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) irq_count = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (irq_count < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (irq_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) port->irq_high = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (port->irq_high < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) port->irq_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) port->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (port->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* the controller clock is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) port->clk = devm_clk_get_optional(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (IS_ERR(port->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return PTR_ERR(port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) err = clk_prepare_enable(port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(&pdev->dev, "Unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) port->power_off = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* disable the interrupt and clear the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel(0, port->base + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel(~0, port->base + GPIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (mxc_gpio_hwtype == IMX21_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Setup one handler for all GPIO interrupts. Actually setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * the handler is needed only once, but doing it for every port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * is more robust and easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* setup one handler for each entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) irq_set_chained_handler_and_data(port->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mx3_gpio_irq_handler, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (port->irq_high > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* setup handler for GPIO 16 to 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) irq_set_chained_handler_and_data(port->irq_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mx3_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err = bgpio_init(&port->gc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) port->base + GPIO_PSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) port->base + GPIO_DR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) port->base + GPIO_GDIR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BGPIOF_READ_OUTPUT_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto out_bgio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) port->gc.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) port->gc.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) port->gc.to_irq = mxc_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pdev->id * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto out_bgio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto out_bgio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!port->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto out_bgio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* gpio-mxc can be a generic irq chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) err = mxc_gpio_init_gc(port, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto out_irqdomain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) list_add_tail(&port->node, &mxc_gpio_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) platform_set_drvdata(pdev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) out_irqdomain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) irq_domain_remove(port->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out_bgio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk_disable_unprepare(port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!port->power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!port->power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int mxc_gpio_syscore_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct mxc_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* walk through all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) list_for_each_entry(port, &mxc_gpio_ports, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mxc_gpio_save_regs(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clk_disable_unprepare(port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void mxc_gpio_syscore_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct mxc_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* walk through all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) list_for_each_entry(port, &mxc_gpio_ports, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = clk_prepare_enable(port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_err("mxc: failed to enable gpio clock %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mxc_gpio_restore_regs(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct syscore_ops mxc_gpio_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .suspend = mxc_gpio_syscore_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .resume = mxc_gpio_syscore_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct platform_driver mxc_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "gpio-mxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .of_match_table = mxc_gpio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .probe = mxc_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .id_table = mxc_gpio_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int __init gpio_mxc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) register_syscore_ops(&mxc_gpio_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return platform_driver_register(&mxc_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) subsys_initcall(gpio_mxc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_DESCRIPTION("i.MX GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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