^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * GPIO driver for Marvell SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This driver is a fairly straightforward GPIO driver for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * complete family of Marvell EBU SoC platforms (Orion, Dove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * driver is the different register layout that exists between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * platforms (MV78200 from the Discovery family and the Armada
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * XP). Therefore, this driver handles three variants of the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - the basic variant, called "orion-gpio", with the simplest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * non-SMP Discovery systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - the mv78200 variant for MV78200 Discovery systems. This variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * turns the edge mask and level mask registers into CPU0 edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * mask/level mask registers, and adds CPU1 edge mask/level mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - the armadaxp variant for Armada XP systems. This variant keeps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the normal cause/edge mask/level mask registers when the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * interrupts are used, but adds per-CPU cause/edge mask/level mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * registers n a separate memory area for the per-CPU GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * GPIO unit register offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_OUT_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_IO_CONF_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_BLINK_EN_OFF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_IN_POL_OFF 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO_DATA_IN_OFF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_EDGE_CAUSE_OFF 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_EDGE_MASK_OFF 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_LEVEL_MASK_OFF 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * PWM register offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PWM_BLINK_ON_DURATION_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PWM_BLINK_OFF_DURATION_OFF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* The MV78200 has per-CPU registers for edge mask and level mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * The Armada XP has per-CPU registers for interrupt cause, interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * mask and interrupt level mask. Those are relative to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * percpu_membase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MVEBU_MAX_GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mvebu_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mvebu_gpio_chip *mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Used to preserve GPIO/PWM registers across suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 blink_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 blink_on_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 blink_off_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mvebu_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regmap *percpu_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int soc_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Used for PWM support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mvebu_pwm *mvpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Used to preserve GPIO registers across suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 out_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 io_conf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 blink_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 in_pol_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 edge_mask_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 level_mask_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Functions returning addresses of individual registers for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct regmap **map, unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (mvchip->soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *map = mvchip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *map = mvchip->percpu_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) regmap_read(map, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_write(map, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct regmap **map, unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) switch (mvchip->soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *map = mvchip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *map = mvchip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *map = mvchip->percpu_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_read(map, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) regmap_write(map, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct regmap **map, unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) switch (mvchip->soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *map = mvchip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *map = mvchip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *map = mvchip->percpu_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mvebu_gpioreg_level_mask(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) regmap_read(map, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mvebu_gpioreg_level_mask(mvchip, &map, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_write(map, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Functions returning addresses of individual registers for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * PWM controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Functions implementing the gpio_chip methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) BIT(pin), value ? BIT(pin) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (u & BIT(pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 data_in, in_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) &in_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u = data_in ^ in_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return (u >> pin) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) BIT(pin), value ? BIT(pin) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Check with the pinctrl driver whether this pin is usable as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * an input GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = pinctrl_gpio_direction_input(chip->base + pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BIT(pin), BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Check with the pinctrl driver whether this pin is usable as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * an output GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = pinctrl_gpio_direction_output(chip->base + pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mvebu_gpio_blink(chip, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mvebu_gpio_set(chip, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BIT(pin), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (u & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return irq_create_mapping(mvchip->domain, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Functions implementing the irq_chip methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void mvebu_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mvebu_gpio_write_edge_cause(mvchip, ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ct->mask_cache_priv &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mvebu_gpio_write_edge_cause(mvchip, ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ct->mask_cache_priv |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void mvebu_gpio_level_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ct->mask_cache_priv &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ct->mask_cache_priv |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * MVEBU GPIO IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * value of the line or the opposite value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Level IRQ handlers: DATA_IN is used directly as cause register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Interrupt are masked by LEVEL_MASK registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Interrupt are masked by EDGE_MASK registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Both-edge handlers: Similar to regular Edge handlers, but also swaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * the polarity to catch the next line transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * This is a race condition that might not perfectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * work on some use cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Every eight GPIO lines are grouped (OR'ed) before going up to main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * cause register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * EDGE cause mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * data-in /--------| |-----| |----\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * -----| |----- ---- to main cause reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * X \----------------| |----/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * polarity LEVEL mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct mvebu_gpio_chip *mvchip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if ((u & BIT(pin)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) type &= IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (type == IRQ_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Check if we need to change chip and handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!(ct->type & type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (irq_setup_alt_chip(d, type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Configure interrupt polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regmap_update_bits(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) BIT(pin), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regmap_update_bits(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) BIT(pin), BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case IRQ_TYPE_EDGE_BOTH: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 data_in, in_pol, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * set initial polarity based on current input level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if ((data_in ^ in_pol) & BIT(pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = BIT(pin); /* falling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val = 0; /* raising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regmap_update_bits(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) BIT(pin), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void mvebu_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (mvchip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) level_mask = mvebu_gpio_read_level_mask(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) edge_cause = mvebu_gpio_read_edge_cause(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) edge_mask = mvebu_gpio_read_edge_mask(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cause = (data_in & level_mask) | (edge_cause & edge_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (i = 0; i < mvchip->chip.ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) irq = irq_find_mapping(mvchip->domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!(cause & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) type = irq_get_trigger_type(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Swap polarity (race with GPIO line) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) polarity ^= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Functions implementing the pwm_chip methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return container_of(chip, struct mvebu_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct gpio_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) spin_lock_irqsave(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (mvpwm->gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) desc = gpiochip_request_own_desc(&mvchip->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pwm->hwpwm, "mvebu-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GPIO_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (IS_ERR(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = PTR_ERR(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mvpwm->gpiod = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_unlock_irqrestore(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spin_lock_irqsave(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) gpiochip_free_own_desc(mvpwm->gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mvpwm->gpiod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) spin_unlock_irqrestore(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void mvebu_pwm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct pwm_state *state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned long long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spin_lock_irqsave(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val = (unsigned long long) u * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) do_div(val, mvpwm->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (val > UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) state->duty_cycle = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) else if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) state->duty_cycle = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) state->duty_cycle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) val = (unsigned long long) u; /* on duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* period = on + off duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val *= NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) do_div(val, mvpwm->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (val > UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) state->period = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) state->period = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) state->period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spin_unlock_irqrestore(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned long long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned int on, off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) do_div(val, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (val > UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) on = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val = (unsigned long long) mvpwm->clk_rate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (state->period - state->duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) do_div(val, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (val > UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) off = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_lock_irqsave(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) spin_unlock_irqrestore(&mvpwm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct pwm_ops mvebu_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .request = mvebu_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .free = mvebu_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .get_state = mvebu_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .apply = mvebu_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct mvebu_pwm *mvpwm = mvchip->mvpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) &mvpwm->blink_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mvpwm->blink_on_duration =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mvpwm->blink_off_duration =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct mvebu_pwm *mvpwm = mvchip->mvpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mvpwm->blink_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) writel_relaxed(mvpwm->blink_on_duration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mvebu_pwmreg_blink_on_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writel_relaxed(mvpwm->blink_off_duration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mvebu_pwmreg_blink_off_duration(mvpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int mvebu_pwm_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct mvebu_gpio_chip *mvchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct mvebu_pwm *mvpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!of_device_is_compatible(mvchip->chip.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "marvell,armada-370-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * There are only two sets of PWM configuration registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * all the GPIO lines on those SoCs which this driver reserves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * for the first two GPIO chips. So if the resource is missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * we can't treat it as an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (IS_ERR(mvchip->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return PTR_ERR(mvchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Use set A for lines of GPIO chip with id 0, B for GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * with id 1. Don't allow further GPIO chips to be used for PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) else if (id == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) set = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!mvpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mvchip->mvpwm = mvpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mvpwm->mvchip = mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (IS_ERR(mvpwm->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return PTR_ERR(mvpwm->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mvpwm->clk_rate = clk_get_rate(mvchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!mvpwm->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mvpwm->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mvpwm->chip.ops = &mvebu_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mvpwm->chip.npwm = mvchip->chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * There may already be some PWM allocated, so we can't force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * mvpwm->chip.base to a fixed point like mvchip->chip.base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * So, we let pwmchip_add() do the numbering and take the next free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mvpwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) spin_lock_init(&mvpwm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return pwmchip_add(&mvpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) cause = mvebu_gpio_read_edge_cause(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) edg_msk = mvebu_gpio_read_edge_mask(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) lvl_msk = mvebu_gpio_read_level_mask(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) for_each_requested_gpio(chip, i, label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) bool is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) msk = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) is_out = !(io_conf & msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (is_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) seq_printf(s, " out %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) out & msk ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) blink & msk ? "(blink )" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) seq_printf(s, " in %s (act %s) - IRQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) (data_in ^ in_pol) & msk ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) in_pol & msk ? "lo" : "hi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!((edg_msk | lvl_msk) & msk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) seq_puts(s, " disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (edg_msk & msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) seq_puts(s, " edge ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (lvl_msk & msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) seq_puts(s, " level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define mvebu_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const struct of_device_id mvebu_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .compatible = "marvell,orion-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .compatible = "marvell,mv78200-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .compatible = "marvell,armadaxp-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .compatible = "marvell,armada-370-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .compatible = "marvell,armada-8k-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &mvchip->out_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &mvchip->io_conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &mvchip->blink_en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &mvchip->in_pol_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) switch (mvchip->soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &mvchip->edge_mask_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &mvchip->level_mask_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GPIO_EDGE_MASK_MV78200_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &mvchip->edge_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) GPIO_LEVEL_MASK_MV78200_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &mvchip->level_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GPIO_EDGE_MASK_ARMADAXP_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &mvchip->edge_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) regmap_read(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &mvchip->level_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (IS_ENABLED(CONFIG_PWM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mvebu_pwm_suspend(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int mvebu_gpio_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mvchip->out_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mvchip->io_conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mvchip->blink_en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mvchip->in_pol_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) switch (mvchip->soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mvchip->edge_mask_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mvchip->level_mask_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GPIO_EDGE_MASK_MV78200_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mvchip->edge_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GPIO_LEVEL_MASK_MV78200_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) mvchip->level_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GPIO_EDGE_MASK_ARMADAXP_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mvchip->edge_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mvchip->level_mask_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (IS_ENABLED(CONFIG_PWM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mvebu_pwm_resume(mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const struct regmap_config mvebu_gpio_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int mvebu_gpio_probe_raw(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) &mvebu_gpio_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (IS_ERR(mvchip->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return PTR_ERR(mvchip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * For the legacy SoCs, the regmap directly maps to the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * registers, so no offset is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mvchip->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * The Armada XP has a second range of registers for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * per-CPU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) mvchip->percpu_regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) &mvebu_gpio_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (IS_ERR(mvchip->percpu_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return PTR_ERR(mvchip->percpu_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct mvebu_gpio_chip *mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (IS_ERR(mvchip->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return PTR_ERR(mvchip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int mvebu_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct mvebu_gpio_chip *mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) unsigned int ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) bool have_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int soc_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int i, cpu, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) soc_variant = (unsigned long) match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Some gpio controllers do not provide irq support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) err = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) have_irqs = err != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (!mvchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) platform_set_drvdata(pdev, mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_err(&pdev->dev, "Missing ngpios OF property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) id = of_alias_get_id(pdev->dev.of_node, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dev_err(&pdev->dev, "Couldn't get OF id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mvchip->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Not all SoCs require a clock.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!IS_ERR(mvchip->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) clk_prepare_enable(mvchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mvchip->soc_variant = soc_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) mvchip->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mvchip->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) mvchip->chip.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mvchip->chip.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mvchip->chip.get_direction = mvebu_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mvchip->chip.direction_input = mvebu_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mvchip->chip.get = mvebu_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mvchip->chip.direction_output = mvebu_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mvchip->chip.set = mvebu_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (have_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mvchip->chip.to_irq = mvebu_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) mvchip->chip.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) mvchip->chip.can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) mvchip->chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) err = mvebu_gpio_probe_syscon(pdev, mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) err = mvebu_gpio_probe_raw(pdev, mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * Mask and clear GPIO interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) switch (soc_variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case MVEBU_GPIO_SOC_VARIANT_ORION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case MVEBU_GPIO_SOC_VARIANT_A8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) case MVEBU_GPIO_SOC_VARIANT_MV78200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) for (cpu = 0; cpu < 2; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) regmap_write(mvchip->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) regmap_write(mvchip->percpu_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) regmap_write(mvchip->percpu_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) regmap_write(mvchip->percpu_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* Some MVEBU SoCs have simple PWM support for GPIO lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (IS_ENABLED(CONFIG_PWM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) err = mvebu_pwm_probe(pdev, mvchip, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Some gpio controllers do not provide irq support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!have_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mvchip->domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!mvchip->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mvchip->chip.label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto err_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) err = irq_alloc_domain_generic_chips(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mvchip->domain, ngpios, 2, np->name, handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mvchip->chip.label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto err_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * NOTE: The common accessors cannot be used because of the percpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * access to the mask registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) gc = irq_get_domain_generic_chip(mvchip->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gc->private = mvchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ct = &gc->chip_types[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ct->chip.name = mvchip->chip.label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ct = &gc->chip_types[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ct->chip.irq_ack = mvebu_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ct->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ct->chip.name = mvchip->chip.label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * Setup the interrupt handlers. Each chip can have up to 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * interrupt handlers, with each handler dealing with 8 GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int irq = platform_get_irq_optional(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) mvchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) err_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) irq_domain_remove(mvchip->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) err_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pwmchip_remove(&mvchip->mvpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct platform_driver mvebu_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .name = "mvebu-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .of_match_table = mvebu_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .probe = mvebu_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .suspend = mvebu_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .resume = mvebu_gpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) builtin_platform_driver(mvebu_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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