^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Medfield MSIC GPIO driver>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2011, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on intel_pmic_gpio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/intel_msic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* the offset for the mapping of global gpio pin to irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MSIC_GPIO_IRQ_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MSIC_GPIO_DIR_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MSIC_GPIO_DIR_OUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MSIC_GPIO_TRIG_FALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MSIC_GPIO_TRIG_RISE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* masks for msic gpio output GPIOxxxxCTLO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSIC_GPIO_DIR_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MSIC_GPIO_DRV_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSIC_GPIO_REN_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSIC_GPIO_DOUT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* masks for msic gpio input GPIOxxxxCTLI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSIC_GPIO_GLBYP_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSIC_GPIO_DIN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSIC_NUM_GPIO 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct msic_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mutex buslock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long trig_change_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned trig_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Both the high and low voltage gpios are divided in two banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int msic_gpio_to_ireg(unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (offset >= MSIC_NUM_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (offset < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return INTEL_MSIC_GPIO0LV0CTLI - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return INTEL_MSIC_GPIO1LV0CTLI - offset + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (offset < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return INTEL_MSIC_GPIO0HV0CTLI - offset + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return INTEL_MSIC_GPIO1HV0CTLI - offset + 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int msic_gpio_to_oreg(unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (offset >= MSIC_NUM_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (offset < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return INTEL_MSIC_GPIO0LV0CTLO - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return INTEL_MSIC_GPIO1LV0CTLO - offset + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (offset < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return INTEL_MSIC_GPIO0HV0CTLO - offset + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return INTEL_MSIC_GPIO1HV0CTLO - offset + 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = msic_gpio_to_oreg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int msic_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) value = (!!value) | MSIC_GPIO_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = msic_gpio_to_oreg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return intel_msic_reg_update(reg, value, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int msic_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg = msic_gpio_to_ireg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = intel_msic_reg_read(reg, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return !!(r & MSIC_GPIO_DIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg = msic_gpio_to_oreg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * This is called from genirq with mg->buslock locked and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * irq_desc->lock held. We can not access the scu bus here, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * store the change and update in the bus_sync_unlock() function below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int msic_irq_type(struct irq_data *data, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 gpio = data->irq - mg->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (gpio >= mg->chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* mark for which gpio the trigger changed, protected by buslock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mg->trig_change_mask |= (1 << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mg->trig_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct msic_gpio *mg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return mg->irq_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void msic_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mutex_lock(&mg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void msic_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 trig = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* We can only get one change at a time as the buslock covers the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) entire transaction. The irq_desc->lock is dropped before we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) called but that is fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (mg->trig_change_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) offset = __ffs(mg->trig_change_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg = msic_gpio_to_ireg(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (mg->trig_type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) trig |= MSIC_GPIO_TRIG_RISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (mg->trig_type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) trig |= MSIC_GPIO_TRIG_FALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mg->trig_change_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mutex_unlock(&mg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Firmware does all the masking and unmasking for us, no masking here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void msic_irq_unmask(struct irq_data *data) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void msic_irq_mask(struct irq_data *data) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct irq_chip msic_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "MSIC-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .irq_mask = msic_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .irq_unmask = msic_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .irq_set_type = msic_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .irq_bus_lock = msic_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .irq_bus_sync_unlock = msic_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void msic_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct irq_data *data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct irq_chip *chip = irq_data_get_irq_chip(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct intel_msic *msic = pdev_to_intel_msic(mg->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int bitnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pending = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for_each_set_bit(bitnr, &pending, BITS_PER_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) generic_handle_irq(mg->irq_base + i * BITS_PER_BYTE + bitnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chip->irq_eoi(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int platform_msic_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct msic_gpio *mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(dev, "no IRQ line: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!pdata || !pdata->gpio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(dev, "incorrect or missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mg = kzalloc(sizeof(*mg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!mg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_set_drvdata(dev, mg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mg->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mg->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mg->chip.label = "msic_gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mg->chip.direction_input = msic_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mg->chip.direction_output = msic_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mg->chip.get = msic_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mg->chip.set = msic_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mg->chip.to_irq = msic_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mg->chip.base = pdata->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mg->chip.ngpio = MSIC_NUM_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mg->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mg->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mutex_init(&mg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) retval = gpiochip_add_data(&mg->chip, mg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(dev, "Adding MSIC gpio chip failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < mg->chip.ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) irq_set_chip_data(i + mg->irq_base, mg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) irq_set_chip_and_handler(i + mg->irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) &msic_irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) kfree(mg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct platform_driver platform_msic_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "msic_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .probe = platform_msic_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int __init platform_msic_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return platform_driver_register(&platform_msic_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) subsys_initcall(platform_msic_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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