Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * version 2.  This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MPC8XXX_GPIO_PINS	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GPIO_DIR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GPIO_ODR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GPIO_DAT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPIO_IER		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GPIO_IMR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GPIO_ICR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPIO_ICR2		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GPIO_IBE		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct mpc8xxx_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct gpio_chip	gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int (*direction_output)(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				unsigned offset, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct irq_domain *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int irqn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * This hardware has a big endian bit assignment such that GPIO line 0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * This inline helper give the right bitmask for a certain line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static inline u32 mpc_pin2mask(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return BIT(31 - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * defined as output cannot be determined by reading GPDAT register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * so we use shadow data register instead. The status of input pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * is determined by reading GPDAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 out_mask, out_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	out_shadow = gc->bgpio_data & out_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return !!((val | out_shadow) & mpc_pin2mask(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* GPIO 28..31 are input only on MPC5121 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (gpio >= 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return mpc8xxx_gc->direction_output(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* GPIO 0..3 are input only on MPC5125 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (gpio <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return mpc8xxx_gc->direction_output(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return irq_create_mapping(mpc8xxx_gc->irq, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	for_each_set_bit(i, &mask, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void mpc8xxx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		| mpc_pin2mask(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void mpc8xxx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		& ~mpc_pin2mask(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void mpc8xxx_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		      mpc_pin2mask(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			| mpc_pin2mask(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			& ~mpc_pin2mask(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	unsigned long gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (gpio < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		reg = mpc8xxx_gc->regs + GPIO_ICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		shift = (15 - gpio) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		reg = mpc8xxx_gc->regs + GPIO_ICR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		shift = (15 - (gpio % 16)) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			| (2 << shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			| (1 << shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct irq_chip mpc8xxx_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.name		= "mpc8xxx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.irq_unmask	= mpc8xxx_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.irq_mask	= mpc8xxx_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.irq_ack	= mpc8xxx_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* this might get overwritten in mpc8xxx_probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.irq_set_type	= mpc8xxx_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	irq_set_chip_data(irq, h->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.map	= mpc8xxx_gpio_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.xlate	= irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mpc8xxx_gpio_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int (*gpio_get)(struct gpio_chip *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int (*irq_set_type)(struct irq_data *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.gpio_dir_out = mpc5121_gpio_dir_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.irq_set_type = mpc512x_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.gpio_dir_out = mpc5125_gpio_dir_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.irq_set_type = mpc512x_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.gpio_get = mpc8572_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.irq_set_type = mpc8xxx_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct of_device_id mpc8xxx_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ .compatible = "fsl,mpc8349-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ .compatible = "fsl,mpc8610-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{ .compatible = "fsl,pq3-gpio",     },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	{ .compatible = "fsl,ls1028a-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ .compatible = "fsl,ls1088a-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ .compatible = "fsl,qoriq-gpio",   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mpc8xxx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct gpio_chip	*gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	const struct mpc8xxx_gpio_devtype *devtype =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (!mpc8xxx_gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	platform_set_drvdata(pdev, mpc8xxx_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	raw_spin_lock_init(&mpc8xxx_gc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	mpc8xxx_gc->regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!mpc8xxx_gc->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	gc = &mpc8xxx_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (of_property_read_bool(np, "little-endian")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		ret = bgpio_init(gc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				 mpc8xxx_gc->regs + GPIO_DAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				 NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				 BGPIOF_BIG_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		ret = bgpio_init(gc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				 mpc8xxx_gc->regs + GPIO_DAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				 NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				 BGPIOF_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 				 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	mpc8xxx_gc->direction_output = gc->direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (!devtype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		devtype = &mpc8xxx_gpio_devtype_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 * It's assumed that only a single type of gpio controller is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 * on the current machine, so overwriting global data is fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (devtype->irq_set_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (devtype->gpio_dir_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		gc->direction_output = devtype->gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (devtype->gpio_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		gc->get = devtype->gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	gc->to_irq = mpc8xxx_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * the input enable of each individual GPIO port.  When an individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * the port value to the GPIO Data Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	    of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	    of_device_is_compatible(np, "fsl,ls1088a-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		pr_err("%pOF: GPIO chip registration failed with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		       np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (!mpc8xxx_gc->irqn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!mpc8xxx_gc->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/* ack and mask all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 			       mpc8xxx_gpio_irq_cascade,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			       IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			       mpc8xxx_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			np->full_name, mpc8xxx_gc->irqn, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (mpc8xxx_gc->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		irq_domain_remove(mpc8xxx_gc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	iounmap(mpc8xxx_gc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int mpc8xxx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (mpc8xxx_gc->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		irq_domain_remove(mpc8xxx_gc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	iounmap(mpc8xxx_gc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_driver mpc8xxx_plat_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.probe		= mpc8xxx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.remove		= mpc8xxx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.name = "gpio-mpc8xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.of_match_table	= mpc8xxx_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int __init mpc8xxx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return platform_driver_register(&mpc8xxx_plat_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) arch_initcall(mpc8xxx_init);