^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC52xx gpio driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static DEFINE_SPINLOCK(gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mpc52xx_gpiochip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct of_mm_gpio_chip mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int shadow_dvo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int shadow_gpioe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int shadow_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * GPIO LIB API implementation for wakeup GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * There's a maximum of 8 wakeup GPIOs. Which of these are available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * for use depends on your board setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 0 -> GPIO_WKUP_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 1 -> GPIO_WKUP_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 2 -> PSC6_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 3 -> PSC6_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 4 -> ETH_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 5 -> PSC3_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 6 -> PSC2_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 7 -> PSC1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) chip->shadow_dvo |= 1 << (7 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) chip->shadow_dvo &= ~(1 << (7 - gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) out_8(®s->wkup_dvo, chip->shadow_dvo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __mpc52xx_wkup_gpio_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* set the direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) chip->shadow_ddr &= ~(1 << (7 - gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) out_8(®s->wkup_ddr, chip->shadow_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* and enable the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) chip->shadow_gpioe |= 1 << (7 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) out_8(®s->wkup_gpioe, chip->shadow_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __mpc52xx_wkup_gpio_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Then set direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) chip->shadow_ddr |= 1 << (7 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) out_8(®s->wkup_ddr, chip->shadow_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Finally enable the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) chip->shadow_gpioe |= 1 << (7 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) out_8(®s->wkup_gpioe, chip->shadow_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mpc52xx_gpiochip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct mpc52xx_gpio_wkup __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) chip = devm_kzalloc(&ofdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) platform_set_drvdata(ofdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) gc = &chip->mmchip.gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) gc->ngpio = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gc->direction_input = mpc52xx_wkup_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gc->direction_output = mpc52xx_wkup_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) gc->get = mpc52xx_wkup_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) gc->set = mpc52xx_wkup_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regs = chip->mmchip.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) chip->shadow_gpioe = in_8(®s->wkup_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->shadow_ddr = in_8(®s->wkup_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) chip->shadow_dvo = in_8(®s->wkup_dvo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int mpc52xx_gpiochip_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct mpc52xx_gpiochip *chip = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) of_mm_gpiochip_remove(&chip->mmchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "fsl,mpc5200-gpio-wkup", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct platform_driver mpc52xx_wkup_gpiochip_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "mpc5200-gpio-wkup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .of_match_table = mpc52xx_wkup_gpiochip_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .probe = mpc52xx_wkup_gpiochip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .remove = mpc52xx_gpiochip_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * GPIO LIB API implementation for simple GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * There's a maximum of 32 simple GPIOs. Which of these are available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * for use depends on your board setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * The numbering reflects the bit numbering in the port registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 0..1 > reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 2..3 > IRDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 4..7 > ETHR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 8..11 > reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 12..15 > USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 16..17 > reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 18..23 > PSC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 24..27 > PSC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 28..31 > PSC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int mpc52xx_simple_gpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = (in_be32(®s->simple_ival) >> (31 - gpio)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) chip->shadow_dvo |= 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) chip->shadow_dvo &= ~(1 << (31 - gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) out_be32(®s->simple_dvo, chip->shadow_dvo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __mpc52xx_simple_gpio_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* set the direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) chip->shadow_ddr &= ~(1 << (31 - gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out_be32(®s->simple_ddr, chip->shadow_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* and enable the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) chip->shadow_gpioe |= 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out_be32(®s->simple_gpioe, chip->shadow_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock_irqsave(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* First set initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __mpc52xx_simple_gpio_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Then set direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) chip->shadow_ddr |= 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) out_be32(®s->simple_ddr, chip->shadow_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Finally enable the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) chip->shadow_gpioe |= 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out_be32(®s->simple_gpioe, chip->shadow_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock_irqrestore(&gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct mpc52xx_gpiochip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct mpc52xx_gpio __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) chip = devm_kzalloc(&ofdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) platform_set_drvdata(ofdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gc = &chip->mmchip.gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gc->ngpio = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) gc->direction_input = mpc52xx_simple_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gc->direction_output = mpc52xx_simple_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gc->get = mpc52xx_simple_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) gc->set = mpc52xx_simple_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regs = chip->mmchip.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chip->shadow_gpioe = in_be32(®s->simple_gpioe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) chip->shadow_ddr = in_be32(®s->simple_ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) chip->shadow_dvo = in_be32(®s->simple_dvo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct of_device_id mpc52xx_simple_gpiochip_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { .compatible = "fsl,mpc5200-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct platform_driver mpc52xx_simple_gpiochip_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "mpc5200-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .of_match_table = mpc52xx_simple_gpiochip_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .probe = mpc52xx_simple_gpiochip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .remove = mpc52xx_gpiochip_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) &mpc52xx_wkup_gpiochip_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &mpc52xx_simple_gpiochip_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int __init mpc52xx_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Make sure we get initialised before anyone else tries to use us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) subsys_initcall(mpc52xx_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void __exit mpc52xx_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) module_exit(mpc52xx_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION("Freescale MPC52xx gpio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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