^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic driver for memory-mapped GPIO controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ...`` ```````..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ..The simplest form of a GPIO controller that the driver supports is``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * `.just a single "data" register, where GPIO state can be read and/or `
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * `````````
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ___
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) `....trivial..'~`.```.```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ```````
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * .```````~~~~`..`.``.``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * . The driver supports `... ,..```.`~~~```````````````....````.``,,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * . big-endian notation, just`. .. A bit more sophisticated controllers ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * . register the device with -be`. .with a pair of set/clear-bit registers ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ``.`.``...``` ```.. output pins are also supported.`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ^^ `````.`````````.,``~``~``~~``````
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * . ^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * .. The expectation is that in at least some cases . ,-~~~-,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * .this will be used with roll-your-own ASIC/FPGA .` \ /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ..````````......``````````` \o_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ^^ / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * ...`````~~`.....``.`..........``````.`.``.```........``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ` 8, 16, 32 and 64 bits registers are supported, and``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * . the number of GPIOs is determined by the width of ~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * `.......````.```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void bgpio_write8(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writeb(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned long bgpio_read8(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return readb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void bgpio_write16(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writew(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned long bgpio_read16(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return readw(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void bgpio_write32(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static unsigned long bgpio_read32(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #if BITS_PER_LONG >= 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void bgpio_write64(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writeq(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static unsigned long bgpio_read64(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return readq(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* BITS_PER_LONG >= 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void bgpio_write16be(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) iowrite16be(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned long bgpio_read16be(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ioread16be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void bgpio_write32be(void __iomem *reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) iowrite32be(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned long bgpio_read32be(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ioread32be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (gc->be_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return BIT(gc->bgpio_bits - 1 - line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return BIT(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long pinmask = bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool dir = !!(gc->bgpio_dir & pinmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return !!(gc->read_reg(gc->reg_set) & pinmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return !!(gc->read_reg(gc->reg_dat) & pinmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * This assumes that the bits in the GPIO register are in native endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * We only assign the function pointer if we have that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long get_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long set_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Make sure we first clear any bits that are zero when we read the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *bits &= ~*mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) set_mask = *mask & gc->bgpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) get_mask = *mask & ~gc->bgpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (set_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *bits |= gc->read_reg(gc->reg_set) & set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (get_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *bits |= gc->read_reg(gc->reg_dat) & get_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * This only works if the bits in the GPIO register are in native endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Make sure we first clear any bits that are zero when we read the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *bits &= ~*mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *bits |= gc->read_reg(gc->reg_dat) & *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * With big endian mirrored bit order it becomes more tedious.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long readmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Make sure we first clear any bits that are zero when we read the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *bits &= ~*mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Create a mirrored mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for_each_set_bit(bit, mask, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) readmask |= bgpio_line2mask(gc, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Read the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val = gc->read_reg(gc->reg_dat) & readmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Mirror the result into the "bits" result, this will give line 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * in bit 0 ... line 31 in bit 31 for a 32bit register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for_each_set_bit(bit, &val, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *bits |= bgpio_line2mask(gc, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long mask = bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gc->bgpio_data |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) gc->bgpio_data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gc->write_reg(gc->reg_dat, gc->bgpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long mask = bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) gc->write_reg(gc->reg_set, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) gc->write_reg(gc->reg_clr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long mask = bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gc->bgpio_data |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gc->bgpio_data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) gc->write_reg(gc->reg_set, gc->bgpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void bgpio_multiple_get_masks(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long *mask, unsigned long *bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long *set_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long *clear_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *set_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *clear_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for_each_set_bit(i, mask, gc->bgpio_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (test_bit(i, bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *set_mask |= bgpio_line2mask(gc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *clear_mask |= bgpio_line2mask(gc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long *bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long set_mask, clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gc->bgpio_data |= set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) gc->bgpio_data &= ~clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) gc->write_reg(reg, gc->bgpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long set_mask, clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (set_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) gc->write_reg(gc->reg_set, set_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (clear_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) gc->write_reg(gc->reg_clr, clear_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) gc->set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (gc->reg_dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (gc->reg_dir_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Return 0 if output, 1 if input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (gc->bgpio_dir_unreadable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (gc->reg_dir_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (gc->reg_dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (gc->reg_dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (gc->reg_dir_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) bgpio_dir_out(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gc->set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gc->set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bgpio_dir_out(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int bgpio_setup_accessors(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool byte_be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (gc->bgpio_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gc->read_reg = bgpio_read8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) gc->write_reg = bgpio_write8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (byte_be) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gc->read_reg = bgpio_read16be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gc->write_reg = bgpio_write16be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) gc->read_reg = bgpio_read16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gc->write_reg = bgpio_write16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (byte_be) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) gc->read_reg = bgpio_read32be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gc->write_reg = bgpio_write32be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gc->read_reg = bgpio_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) gc->write_reg = bgpio_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #if BITS_PER_LONG >= 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (byte_be) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "64 bit big endian byte order unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gc->read_reg = bgpio_read64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) gc->write_reg = bgpio_write64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif /* BITS_PER_LONG >= 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Create the device and allocate the resources. For setting GPIO's there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * three supported configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * - single input/output register resource (named "dat").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * - set/clear pair (named "set" and "clr").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * - single output register resource and single input resource ("set" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * dat").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * For the single output register, this drives a 1 by setting a bit and a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * in the set register and clears it by setting a bit in the clear register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * The configuration is detected by which resources are present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * For setting the GPIO direction, there are three supported configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * - simple bidirection GPIO that requires no configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * - an output direction register (named "dirout") where a 1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * indicates the GPIO is an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * - an input direction register (named "dirin") where a 1 bit indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * the GPIO is an input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int bgpio_setup_io(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) void __iomem *dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void __iomem *set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void __iomem *clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gc->reg_dat = dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!gc->reg_dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (set && clr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gc->reg_set = set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) gc->reg_clr = clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gc->set = bgpio_set_with_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) gc->set_multiple = bgpio_set_multiple_with_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else if (set && !clr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) gc->reg_set = set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) gc->set = bgpio_set_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) gc->set_multiple = bgpio_set_multiple_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else if (flags & BGPIOF_NO_OUTPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) gc->set = bgpio_set_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) gc->set_multiple = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) gc->set = bgpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) gc->set_multiple = bgpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) gc->get = bgpio_get_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!gc->be_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) gc->get_multiple = bgpio_get_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * We deliberately avoid assigning the ->get_multiple() call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * for big endian mirrored registers which are ALSO reflecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * their value in the set register when used as output. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * simply too much complexity, let the GPIO core fall back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * reading each line individually in that fringe case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) gc->get = bgpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (gc->be_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) gc->get_multiple = bgpio_get_multiple_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) gc->get_multiple = bgpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int bgpio_setup_direction(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void __iomem *dirout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void __iomem *dirin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (dirout || dirin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gc->reg_dir_out = dirout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gc->reg_dir_in = dirin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (flags & BGPIOF_NO_SET_ON_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) gc->direction_output = bgpio_dir_out_dir_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) gc->direction_output = bgpio_dir_out_val_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) gc->direction_input = bgpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) gc->get_direction = bgpio_get_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (flags & BGPIOF_NO_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) gc->direction_output = bgpio_dir_out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) gc->direction_output = bgpio_simple_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) gc->direction_input = bgpio_simple_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (gpio_pin < chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * bgpio_init() - Initialize generic GPIO accessor functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * @gc: the GPIO chip to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @dev: the parent device of the new GPIO chip (compulsory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * @dat: MMIO address for the register to READ the value of the GPIO lines, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * is expected that a 1 in the corresponding bit in this register means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * line is asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * @set: MMIO address for the register to SET the value of the GPIO lines, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * expected that we write the line with 1 in this register to drive the GPIO line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * expected that we write the line with 1 in this register to drive the GPIO line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * low. It is allowed to leave this address as NULL, in that case the SET register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * will be assumed to also clear the GPIO lines, by actively writing the line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * with 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * that setting a line to 1 in this register will turn that line into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * output line. Conversely, setting the line to 0 will turn that line into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * an input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * that setting a line to 1 in this register will turn that line into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * input line. Conversely, setting the line to 0 will turn that line into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @flags: Different flags that will affect the behaviour of the device, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * endianness etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int bgpio_init(struct gpio_chip *gc, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned long sz, void __iomem *dat, void __iomem *set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!is_power_of_2(sz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) gc->bgpio_bits = sz * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (gc->bgpio_bits > BITS_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) spin_lock_init(&gc->bgpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) gc->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) gc->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) gc->ngpio = gc->bgpio_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) gc->request = bgpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = bgpio_setup_io(gc, dat, set, clr, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = bgpio_setup_direction(gc, dirout, dirin, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) gc->bgpio_data = gc->read_reg(gc->reg_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (gc->set == bgpio_set_set &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) !(flags & BGPIOF_UNREADABLE_REG_SET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) gc->bgpio_data = gc->read_reg(gc->reg_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (flags & BGPIOF_UNREADABLE_REG_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) gc->bgpio_dir_unreadable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Inspect hardware to find initial direction setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((gc->reg_dir_out || gc->reg_dir_in) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (gc->reg_dir_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else if (gc->reg_dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * If we have two direction registers, synchronise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * input setting to output setting, the library
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * can not handle a line being input and output at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (gc->reg_dir_out && gc->reg_dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) EXPORT_SYMBOL_GPL(bgpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void __iomem *bgpio_map(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) resource_size_t sane_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) resource_size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) sz = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (sz != sane_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return IOMEM_ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct of_device_id bgpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { .compatible = "brcm,bcm6345-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { .compatible = "wd,mbl-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { .compatible = "ni,169445-nand-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MODULE_DEVICE_TABLE(of, bgpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct bgpio_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!of_match_device(bgpio_of_match, &pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pdata->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (of_device_is_big_endian(pdev->dev.of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (of_property_read_bool(pdev->dev.of_node, "no-output"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) *flags |= BGPIOF_NO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int bgpio_pdev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) void __iomem *dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) void __iomem *set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) void __iomem *clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) void __iomem *dirout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void __iomem *dirin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct bgpio_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pdata = bgpio_parse_dt(pdev, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) flags = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) sz = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dat = bgpio_map(pdev, "dat", sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (IS_ERR(dat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return PTR_ERR(dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) set = bgpio_map(pdev, "set", sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (IS_ERR(set))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return PTR_ERR(set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) clr = bgpio_map(pdev, "clr", sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (IS_ERR(clr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return PTR_ERR(clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dirout = bgpio_map(pdev, "dirout", sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (IS_ERR(dirout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return PTR_ERR(dirout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dirin = bgpio_map(pdev, "dirin", sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (IS_ERR(dirin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return PTR_ERR(dirin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (pdata->label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) gc->label = pdata->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) gc->base = pdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (pdata->ngpio > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) gc->ngpio = pdata->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) platform_set_drvdata(pdev, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const struct platform_device_id bgpio_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "basic-mmio-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .driver_data = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .name = "basic-mmio-gpio-be",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .driver_data = BGPIOF_BIG_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MODULE_DEVICE_TABLE(platform, bgpio_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static struct platform_driver bgpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "basic-mmio-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .of_match_table = of_match_ptr(bgpio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .id_table = bgpio_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .probe = bgpio_pdev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) module_platform_driver(bgpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags