Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * There are 3 YU GPIO blocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * gpio[0]: HOST_GPIO0->HOST_GPIO31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * gpio[1]: HOST_GPIO32->HOST_GPIO63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * gpio[2]: HOST_GPIO64->HOST_GPIO69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * arm_gpio_lock register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * bit[31]	lock status: active if set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * bit[15:0]	set lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * The lock is enabled only if 0xd42f is written to this field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define YU_ARM_GPIO_LOCK_ADDR		0x2801088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define YU_ARM_GPIO_LOCK_SIZE		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define YU_LOCK_ACTIVE_BIT(val)		(val >> 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define YU_ARM_GPIO_LOCK_ACQUIRE	0xd42f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define YU_ARM_GPIO_LOCK_RELEASE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * gpio[x] block registers and their offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define YU_GPIO_DATAIN			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define YU_GPIO_MODE1			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define YU_GPIO_MODE0			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define YU_GPIO_DATASET			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define YU_GPIO_DATACLEAR		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define YU_GPIO_MODE1_CLEAR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define YU_GPIO_MODE0_SET		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define YU_GPIO_MODE0_CLEAR		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct mlxbf2_gpio_context_save_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 gpio_mode0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 gpio_mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* BlueField-2 gpio block context structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct mlxbf2_gpio_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* YU GPIO blocks address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem *gpio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct mlxbf2_gpio_context_save_regs *csave_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* BlueField-2 gpio shared structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct mlxbf2_gpio_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	void __iomem *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct mutex *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static struct resource yu_arm_gpio_lock_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.start = YU_ARM_GPIO_LOCK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.end   = YU_ARM_GPIO_LOCK_ADDR + YU_ARM_GPIO_LOCK_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.name  = "YU_ARM_GPIO_LOCK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.res = &yu_arm_gpio_lock_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.lock = &yu_arm_gpio_lock_mutex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* Request memory region and map yu_arm_gpio_lock resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	mutex_lock(yu_arm_gpio_lock_param.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Check if the memory map already exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (yu_arm_gpio_lock_param.io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	res = yu_arm_gpio_lock_param.res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!devm_request_mem_region(dev, res->start, size, res->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (!yu_arm_gpio_lock_param.io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mutex_unlock(yu_arm_gpio_lock_param.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * Acquire the YU arm_gpio_lock to be able to change the direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * mode. If the lock_active bit is already set, return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 arm_gpio_lock_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mutex_lock(yu_arm_gpio_lock_param.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spin_lock(&gs->gc.bgpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * When lock active bit[31] is set, ModeX is write enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		spin_unlock(&gs->gc.bgpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		mutex_unlock(yu_arm_gpio_lock_param.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * Release the YU arm_gpio_lock after changing the direction mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	__releases(&gs->gc.bgpio_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	__releases(yu_arm_gpio_lock_param.lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_unlock(&gs->gc.bgpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mutex_unlock(yu_arm_gpio_lock_param.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * mode0 and mode1 are both locked by the gpio_lock field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * Together, mode0 and mode1 define the gpio Mode dependeing also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * on Reg_DataOut.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * Set input direction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * {mode1,mode0} = {0,0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				       unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * Although the arm_gpio_lock was set in the probe function, check again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * if it is still enabled to be able to write to the ModeX registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ret = mlxbf2_gpio_lock_acquire(gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mlxbf2_gpio_lock_release(gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * Set output direction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * {mode1,mode0} = {0,1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * Although the arm_gpio_lock was set in the probe function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * check again it is still enabled to be able to write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * ModeX registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = mlxbf2_gpio_lock_acquire(gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mlxbf2_gpio_lock_release(gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* BlueField-2 GPIO driver initialization routine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mlxbf2_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct mlxbf2_gpio_context *gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* YU GPIO block address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!gs->gpio_io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = mlxbf2_gpio_get_lock_res(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (device_property_read_u32(dev, "npins", &npins))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	gc = &gs->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ret = bgpio_init(gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			gs->gpio_io + YU_GPIO_DATAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			gs->gpio_io + YU_GPIO_DATASET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			gs->gpio_io + YU_GPIO_DATACLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_err(dev, "bgpio_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	gc->direction_input = mlxbf2_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	gc->direction_output = mlxbf2_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	gc->ngpio = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	platform_set_drvdata(pdev, gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		dev_err(dev, "Failed adding memory mapped gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int mlxbf2_gpio_suspend(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		YU_GPIO_MODE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		YU_GPIO_MODE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int mlxbf2_gpio_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		YU_GPIO_MODE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		YU_GPIO_MODE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{ "MLNXBF22", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct platform_driver mlxbf2_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.name = "mlxbf2_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.acpi_match_table = ACPI_PTR(mlxbf2_gpio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.probe    = mlxbf2_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.suspend  = mlxbf2_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.resume   = mlxbf2_gpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) module_platform_driver(mlxbf2_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_AUTHOR("Mellanox Technologies");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_LICENSE("GPL v2");