^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IOH_EDGE_FALLING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IOH_EDGE_RISING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IOH_LEVEL_L BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IOH_LEVEL_H (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IOH_EDGE_BOTH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IOH_IRQ_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct ioh_reg_comn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 istatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 idisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 imaskclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 po;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 im_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 im_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ioh_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ioh_reg_comn regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 reserve1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 ioh_sel_reg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 reserve2[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 srst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * struct ioh_gpio_reg_data - The register store data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @ien_reg: To store contents of interrupt enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @imask_reg: To store contents of interrupt mask regist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @po_reg: To store contents of PO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @pm_reg: To store contents of PM register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @im0_reg: To store contents of interrupt mode regist0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @im1_reg: To store contents of interrupt mode regist1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct ioh_gpio_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 ien_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 imask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 po_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 pm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 im0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 im1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 use_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * struct ioh_gpio - GPIO private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @base: PCI base address of Memory mapped I/O register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @reg: Memory mapped IOH GPIO register list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @dev: Pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @gpio: Data for GPIO infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @ioh_gpio_reg: Memory mapped Register data is saved here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * when suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @ch: Indicate GPIO channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @irq_base: Save base of IRQ number for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @spinlock: Used for register access protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ioh_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ioh_regs __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct ioh_gpio_reg_data ioh_gpio_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 gpio_use_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spinlock_t spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ioh_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg_val = ioread32(&chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg_val |= (1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg_val &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ioh_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct ioh_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pm = ioread32(&chip->reg->regs[chip->ch].pm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ((1 << num_ports[chip->ch]) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pm |= (1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) iowrite32(pm, &chip->reg->regs[chip->ch].pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg_val = ioread32(&chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg_val |= (1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg_val &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ioh_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pm = ioread32(&chip->reg->regs[chip->ch].pm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ((1 << num_ports[chip->ch]) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pm &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) iowrite32(pm, &chip->reg->regs[chip->ch].pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Save register configuration and disable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (i = 0; i < 8; i ++, chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) chip->ioh_gpio_reg.po_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ioread32(&chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chip->ioh_gpio_reg.pm_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ioread32(&chip->reg->regs[chip->ch].pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) chip->ioh_gpio_reg.ien_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ioread32(&chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) chip->ioh_gpio_reg.imask_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ioread32(&chip->reg->regs[chip->ch].imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chip->ioh_gpio_reg.im0_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ioread32(&chip->reg->regs[chip->ch].im_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) chip->ioh_gpio_reg.im1_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ioread32(&chip->reg->regs[chip->ch].im_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chip->ioh_gpio_reg.use_sel_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ioread32(&chip->reg->ioh_sel_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * This function restores the register configuration of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (i = 0; i < 8; i ++, chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) iowrite32(chip->ioh_gpio_reg.po_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &chip->reg->regs[chip->ch].po);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) iowrite32(chip->ioh_gpio_reg.pm_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &chip->reg->regs[chip->ch].pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) iowrite32(chip->ioh_gpio_reg.ien_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iowrite32(chip->ioh_gpio_reg.imask_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &chip->reg->regs[chip->ch].imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iowrite32(chip->ioh_gpio_reg.im0_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) &chip->reg->regs[chip->ch].im_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) iowrite32(chip->ioh_gpio_reg.im1_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &chip->reg->regs[chip->ch].im_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iowrite32(chip->ioh_gpio_reg.use_sel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &chip->reg->ioh_sel_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ioh_gpio *chip = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return chip->irq_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct gpio_chip *gpio = &chip->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) gpio->label = dev_name(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) gpio->direction_input = ioh_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) gpio->get = ioh_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gpio->direction_output = ioh_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) gpio->set = ioh_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) gpio->dbg_show = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) gpio->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gpio->ngpio = num_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) gpio->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) gpio->to_irq = ioh_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int ioh_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 im;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *im_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 im_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ioh_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ch = irq - chip->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (irq <= chip->irq_base + 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) im_reg = &chip->reg->regs[chip->ch].im_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) im_pos = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) im_reg = &chip->reg->regs[chip->ch].im_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) im_pos = ch - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __func__, irq, type, ch, im_pos, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val = IOH_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val = IOH_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = IOH_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val = IOH_LEVEL_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val = IOH_LEVEL_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case IRQ_TYPE_PROBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_warn(chip->dev, "%s: unknown type(%dd)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __func__, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Set interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) iowrite32(im | (val << (im_pos * 4)), im_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* iclr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* IMASKCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ien = ioread32(&chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void ioh_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct ioh_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) iowrite32(1 << (d->irq - chip->irq_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &chip->reg->regs[chip->ch].imaskclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void ioh_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct ioh_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) iowrite32(1 << (d->irq - chip->irq_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) &chip->reg->regs[chip->ch].imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void ioh_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct ioh_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ien = ioread32(&chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ien &= ~(1 << (d->irq - chip->irq_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) iowrite32(ien, &chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void ioh_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ioh_gpio *chip = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ien = ioread32(&chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ien |= 1 << (d->irq - chip->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) iowrite32(ien, &chip->reg->regs[chip->ch].ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ioh_gpio *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; i < 8; i++, chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg_val = ioread32(&chip->reg->regs[i].istatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (j = 0; j < num_ports[i]; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (reg_val & BIT(j)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_dbg(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "%s:[%d]:irq=%d status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __func__, j, irq, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) iowrite32(BIT(j),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &chip->reg->regs[chip->ch].iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) generic_handle_irq(chip->irq_base + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) chip->base, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) gc->private = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ct->chip.irq_mask = ioh_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ct->chip.irq_unmask = ioh_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ct->chip.irq_set_type = ioh_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ct->chip.irq_disable = ioh_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ct->chip.irq_enable = ioh_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) IRQ_GC_INIT_MASK_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) IRQ_NOREQUEST | IRQ_NOPROBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int ioh_gpio_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct ioh_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void *chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto err_pci_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = pci_request_regions(pdev, KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto err_request_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) base = pci_iomap(pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (chip_save == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto err_kzalloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) chip = chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (i = 0; i < 8; i++, chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) chip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) chip->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chip->reg = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) chip->ch = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spin_lock_init(&chip->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ioh_gpio_setup(chip, num_ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = gpiochip_add_data(&chip->gpio, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto err_gpiochip_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) chip = chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (j = 0; j < 8; j++, chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) num_ports[j], NUMA_NO_NODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "ml_ioh_gpio: Failed to get IRQ base num\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto err_gpiochip_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) chip->irq_base = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = ioh_gpio_alloc_generic_chip(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) irq_base, num_ports[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto err_gpiochip_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) chip = chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) IRQF_SHARED, KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "%s request_irq failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err_gpiochip_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err_gpiochip_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) chip = chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gpiochip_remove(&chip->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) chip++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) kfree(chip_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err_kzalloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_iounmap(pdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err_request_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err_pci_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void ioh_gpio_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct ioh_gpio *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) void *chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) chip_save = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = 0; i < 8; i++, chip++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gpiochip_remove(&chip->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) chip = chip_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pci_iounmap(pdev, chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct ioh_gpio *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ioh_gpio_save_reg_conf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = pci_enable_wake(pdev, PCI_D0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int ioh_gpio_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ioh_gpio *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = pci_enable_wake(pdev, PCI_D0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spin_lock_irqsave(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) iowrite32(0x01, &chip->reg->srst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) iowrite32(0x00, &chip->reg->srst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ioh_gpio_restore_reg_conf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spin_unlock_irqrestore(&chip->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ioh_gpio_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define ioh_gpio_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct pci_device_id ioh_gpio_pcidev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct pci_driver ioh_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "ml_ioh_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .id_table = ioh_gpio_pcidev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .probe = ioh_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .remove = ioh_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .suspend = ioh_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .resume = ioh_gpio_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) module_pci_driver(ioh_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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