^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Merrifield SoC GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GCCR 0x000 /* controller configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GPLR 0x004 /* pin level r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GPDR 0x01c /* pin direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GPSR 0x034 /* pin set w/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GPCR 0x04c /* pin clear w/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GRER 0x064 /* rising edge detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GFER 0x07c /* falling edge detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GFBR 0x094 /* glitch filter bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GIMR 0x0ac /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GISR 0x0c4 /* interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GITR 0x300 /* input type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GLPR 0x318 /* level input polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GWMR 0x400 /* wake mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GWSR 0x418 /* wake source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GSIR 0xc00 /* secure input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Intel Merrifield has 192 GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MRFLD_NGPIO 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mrfld_gpio_pinrange {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_PINRANGE(gstart, gend, pstart) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .gpio_base = (gstart), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .pin_base = (pstart), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .npins = (gend) - (gstart) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mrfld_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GPIO_PINRANGE(0, 11, 146),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GPIO_PINRANGE(12, 13, 144),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GPIO_PINRANGE(14, 15, 35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GPIO_PINRANGE(16, 16, 164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GPIO_PINRANGE(17, 18, 105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GPIO_PINRANGE(19, 22, 101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GPIO_PINRANGE(23, 30, 107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GPIO_PINRANGE(32, 43, 67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GPIO_PINRANGE(44, 63, 195),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GPIO_PINRANGE(64, 67, 140),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GPIO_PINRANGE(68, 69, 165),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GPIO_PINRANGE(70, 71, 65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GPIO_PINRANGE(72, 76, 228),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GPIO_PINRANGE(77, 86, 37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GPIO_PINRANGE(87, 87, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GPIO_PINRANGE(88, 88, 47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GPIO_PINRANGE(89, 96, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GPIO_PINRANGE(97, 97, 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GPIO_PINRANGE(102, 119, 83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GPIO_PINRANGE(120, 123, 79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GPIO_PINRANGE(124, 135, 115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GPIO_PINRANGE(137, 142, 158),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GPIO_PINRANGE(154, 163, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GPIO_PINRANGE(164, 176, 215),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GPIO_PINRANGE(177, 189, 127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GPIO_PINRANGE(190, 191, 178),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int reg_type_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 reg = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return priv->reg_base + reg_type_offset + reg * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *gplr = gpio_reg(chip, offset, GPLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return !!(readl(gplr) & BIT(offset % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *gpsr, *gpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gpsr = gpio_reg(chip, offset, GPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(BIT(offset % 32), gpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) gpcr = gpio_reg(chip, offset, GPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(BIT(offset % 32), gpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int mrfld_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) value = readl(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) value &= ~BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(value, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int mrfld_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mrfld_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) value = readl(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) value |= BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(value, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (readl(gpdr) & BIT(offset % 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) value = readl(gfbr) & ~BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) value = readl(gfbr) | BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(value, gfbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return mrfld_gpio_set_debounce(chip, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void mrfld_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(BIT(gpio % 32), gisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) value = readl(gimr) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) value = readl(gimr) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(value, gimr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void mrfld_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mrfld_irq_unmask_mask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void mrfld_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mrfld_irq_unmask_mask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mrfld_gpio *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) value = readl(grer) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) value = readl(grer) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(value, grer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) value = readl(gfer) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) value = readl(gfer) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(value, gfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * To prevent glitches from triggering an unintended level interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * configure GLPR register first and then configure GITR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (type & IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) value = readl(glpr) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) value = readl(glpr) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(value, glpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (type & IRQ_TYPE_LEVEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) value = readl(gitr) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(value, gitr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } else if (type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) value = readl(gitr) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(value, gitr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct mrfld_gpio *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) raw_spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Clear the existing wake status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel(BIT(gpio % 32), gwsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) value = readl(gwmr) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) value = readl(gwmr) & ~BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(value, gwmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) raw_spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct irq_chip mrfld_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "gpio-merrifield",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .irq_ack = mrfld_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .irq_mask = mrfld_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .irq_unmask = mrfld_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .irq_set_type = mrfld_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .irq_set_wake = mrfld_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void mrfld_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mrfld_gpio *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long base, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Check GPIO controller to check which pin triggered the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (base = 0; base < priv->chip.ngpio; base += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long pending, enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pending = readl(gisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) enabled = readl(gimr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Only interrupts that are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pending &= enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for_each_set_bit(gpio, &pending, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) irq = irq_find_mapping(gc->irq.domain, base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int mrfld_irq_init_hw(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (base = 0; base < priv->chip.ngpio; base += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Clear the rising-edge detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) reg = gpio_reg(&priv->chip, base, GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Clear the falling-edge detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) reg = gpio_reg(&priv->chip, base, GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (adev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) acpi_dev_put(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) name = "pinctrl-merrifield";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mrfld_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const struct mrfld_gpio_pinrange *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const char *pinctrl_dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) range = &mrfld_gpio_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) range->gpio_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) range->pin_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) range->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(priv->dev, "failed to add GPIO pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mrfld_gpio *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 gpio_base, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) retval = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(&pdev->dev, "I/O memory mapping error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) base = pcim_iomap_table(pdev)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) irq_base = readl(base + 0 * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) gpio_base = readl(base + 1 * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Release the IO mapping, since we already get the info from BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pcim_iounmap_regions(pdev, BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) priv->reg_base = pcim_iomap_table(pdev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) priv->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) priv->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) priv->chip.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) priv->chip.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) priv->chip.direction_input = mrfld_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) priv->chip.direction_output = mrfld_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) priv->chip.get = mrfld_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) priv->chip.set = mrfld_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) priv->chip.get_direction = mrfld_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) priv->chip.set_config = mrfld_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) priv->chip.base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) priv->chip.ngpio = MRFLD_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) priv->chip.can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) raw_spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) girq = &priv->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) girq->chip = &mrfld_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) girq->init_hw = mrfld_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) girq->parent_handler = mrfld_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) sizeof(*girq->parents), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) girq->parents[0] = pci_irq_vector(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) girq->first = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct pci_device_id mrfld_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { PCI_VDEVICE(INTEL, 0x1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct pci_driver mrfld_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "gpio-merrifield",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .id_table = mrfld_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .probe = mrfld_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) module_pci_driver(mrfld_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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