^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MC33880 high-side/low-side switch GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Freescale MC33880 high-side/low-side switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/mc33880.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRIVER_NAME "mc33880"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Pin configurations, see MAX7301 datasheet page 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIN_CONFIG_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIN_CONFIG_IN_PULLUP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PIN_CONFIG_IN_WO_PULLUP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIN_CONFIG_OUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PIN_NUMBER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Some registers must be read back to modify.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * To save time we cache them here in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mc33880 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mutex lock; /* protect from simultaneous accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 port_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int mc33880_write_config(struct mc33880 *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return spi_write(mc->spi, &mc->port_config, sizeof(mc->port_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int __mc33880_set(struct mc33880 *mc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mc->port_config |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mc->port_config &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return mc33880_write_config(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void mc33880_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mc33880 *mc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mutex_lock(&mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __mc33880_set(mc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mutex_unlock(&mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int mc33880_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mc33880 *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mc33880_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!pdata || !pdata->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_dbg(&spi->dev, "incorrect or missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * bits_per_word cannot be configured in platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mc = devm_kzalloc(&spi->dev, sizeof(struct mc33880), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_init(&mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spi_set_drvdata(spi, mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mc->chip.label = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mc->chip.set = mc33880_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mc->chip.base = pdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mc->chip.ngpio = PIN_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mc->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mc->chip.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mc->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mc->port_config = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* write twice, because during initialisation the first setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * is just for testing SPI communication, and the second is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * "real" configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = mc33880_write_config(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mc->port_config = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = mc33880_write_config(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&spi->dev, "Failed writing to " DRIVER_NAME ": %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) goto exit_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = gpiochip_add_data(&mc->chip, mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto exit_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) exit_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mutex_destroy(&mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int mc33880_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mc33880 *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mc = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) gpiochip_remove(&mc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mutex_destroy(&mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct spi_driver mc33880_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .probe = mc33880_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .remove = mc33880_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int __init mc33880_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return spi_register_driver(&mc33880_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* register after spi postcore initcall and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * subsys initcalls that may rely on these GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) subsys_initcall(mc33880_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __exit mc33880_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spi_unregister_driver(&mc33880_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) module_exit(mc33880_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_AUTHOR("Mocean Laboratories <info@mocean-labs.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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