Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/drivers/gpio/gpio-mb86s7x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2015 Fujitsu Semiconductor Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "gpiolib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "gpiolib-acpi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Only first 8bits of a register correspond to each pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * so there are 4 registers for 32 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PDR(x)	(0x0 + x / 8 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DDR(x)	(0x10 + x / 8 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PFR(x)	(0x20 + x / 8 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OFFSET(x)	BIT((x) % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct mb86s70_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	spin_lock_irqsave(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	val = readl(gchip->base + PFR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	val &= ~OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	writel(val, gchip->base + PFR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	spin_unlock_irqrestore(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	spin_lock_irqsave(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	val = readl(gchip->base + PFR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	val |= OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writel(val, gchip->base + PFR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	spin_unlock_irqrestore(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spin_lock_irqsave(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	val = readl(gchip->base + DDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	val &= ~OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(val, gchip->base + DDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	spin_unlock_irqrestore(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 					 unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_lock_irqsave(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	val = readl(gchip->base + PDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		val |= OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		val &= ~OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writel(val, gchip->base + PDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	val = readl(gchip->base + DDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	val |= OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writel(val, gchip->base + DDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_unlock_irqrestore(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spin_lock_irqsave(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	val = readl(gchip->base + PDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		val |= OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		val &= ~OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel(val, gchip->base + PDR(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	spin_unlock_irqrestore(&gchip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int irq, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	for (index = 0;; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		irq = platform_get_irq(to_platform_device(gc->parent), index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (irq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		if (irq_get_irq_data(irq)->hwirq == offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int mb86s70_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct mb86s70_gpio_chip *gchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (gchip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	platform_set_drvdata(pdev, gchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	gchip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (IS_ERR(gchip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return PTR_ERR(gchip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	gchip->clk = devm_clk_get_optional(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (IS_ERR(gchip->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return PTR_ERR(gchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = clk_prepare_enable(gchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	spin_lock_init(&gchip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	gchip->gc.direction_output = mb86s70_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	gchip->gc.direction_input = mb86s70_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	gchip->gc.request = mb86s70_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	gchip->gc.free = mb86s70_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	gchip->gc.get = mb86s70_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	gchip->gc.set = mb86s70_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	gchip->gc.to_irq = mb86s70_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	gchip->gc.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	gchip->gc.ngpio = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	gchip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	gchip->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	gchip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = gpiochip_add_data(&gchip->gc, gchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dev_err(&pdev->dev, "couldn't register gpio driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		clk_disable_unprepare(gchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	acpi_gpiochip_request_interrupts(&gchip->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int mb86s70_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	acpi_gpiochip_free_interrupts(&gchip->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	gpiochip_remove(&gchip->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	clk_disable_unprepare(gchip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct of_device_id mb86s70_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	{ .compatible = "fujitsu,mb86s70-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ "SCX0007" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct platform_driver mb86s70_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.name = "mb86s70-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.of_match_table = mb86s70_gpio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.probe = mb86s70_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.remove = mb86s70_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) module_platform_driver(mb86s70_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DESCRIPTION("MB86S7x GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_ALIAS("platform:mb86s70-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_LICENSE("GPL");