^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2018 BayLibre SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // GPIO driver for MAXIM 77650/77651 charger/power-supply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/max77650.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX77650_GPIO_DIR_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX77650_GPIO_INVAL_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX77650_GPIO_DRV_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX77650_GPIO_OUTVAL_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX77650_GPIO_DEBOUNCE_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX77650_GPIO_DIR_OUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX77650_GPIO_DIR_IN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAX77650_GPIO_OUT_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX77650_GPIO_OUT_HIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX77650_GPIO_DRV_OPEN_DRAIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX77650_GPIO_DRV_PUSH_PULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX77650_GPIO_DEBOUNCE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX77650_GPIO_DIR_BITS(_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ((_reg) & MAX77650_GPIO_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX77650_GPIO_INVAL_BITS(_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (((_reg) & MAX77650_GPIO_INVAL_MASK) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct max77650_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int max77650_gpio_direction_input(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return regmap_update_bits(chip->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MAX77650_REG_CNFG_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MAX77650_GPIO_DIR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MAX77650_GPIO_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int max77650_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int mask, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mask = MAX77650_GPIO_DIR_MASK | MAX77650_GPIO_OUTVAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) regval |= MAX77650_GPIO_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return regmap_update_bits(chip->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MAX77650_REG_CNFG_GPIO, mask, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void max77650_gpio_set_value(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int rv, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) rv = regmap_update_bits(chip->map, MAX77650_REG_CNFG_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MAX77650_GPIO_OUTVAL_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_err(gc->parent, "cannot set GPIO value: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int max77650_gpio_get_value(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return MAX77650_GPIO_INVAL_BITS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int max77650_gpio_get_direction(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return MAX77650_GPIO_DIR_BITS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int max77650_gpio_set_config(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int offset, unsigned long cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (pinconf_to_config_param(cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return regmap_update_bits(chip->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MAX77650_REG_CNFG_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MAX77650_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MAX77650_GPIO_DRV_OPEN_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return regmap_update_bits(chip->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MAX77650_REG_CNFG_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MAX77650_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MAX77650_GPIO_DRV_PUSH_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return regmap_update_bits(chip->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MAX77650_REG_CNFG_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MAX77650_GPIO_DEBOUNCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MAX77650_GPIO_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int max77650_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct max77650_gpio_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int max77650_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct max77650_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device *dev, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) i2c = to_i2c_client(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) chip->map = dev_get_regmap(parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!chip->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) chip->irq = platform_get_irq_byname(pdev, "GPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) chip->gc.ngpio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) chip->gc.label = i2c->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) chip->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) chip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) chip->gc.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chip->gc.direction_input = max77650_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip->gc.direction_output = max77650_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) chip->gc.set = max77650_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) chip->gc.get = max77650_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) chip->gc.get_direction = max77650_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) chip->gc.set_config = max77650_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chip->gc.to_irq = max77650_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return devm_gpiochip_add_data(dev, &chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver max77650_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "max77650-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .probe = max77650_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) module_platform_driver(max77650_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DESCRIPTION("MAXIM 77650/77651 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_ALIAS("platform:max77650-gpio");
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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