^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MAXIM MAX77620 GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct max77620_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct regmap *rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mutex buslock; /* irq_bus_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int irq_type[MAX77620_GPIO_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool irq_enabled[MAX77620_GPIO_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct max77620_gpio *gpio = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int value, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pending = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) handle_nested_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void max77620_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct max77620_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) gpio->irq_enabled[data->hwirq] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void max77620_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct max77620_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) gpio->irq_enabled[data->hwirq] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct max77620_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) irq_type = MAX77620_CNFG_GPIO_INT_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) irq_type = MAX77620_CNFG_GPIO_INT_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MAX77620_CNFG_GPIO_INT_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) gpio->irq_type[data->hwirq] = irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void max77620_gpio_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct max77620_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mutex_lock(&gpio->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct max77620_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int value, offset = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MAX77620_CNFG_GPIO_INT_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(chip->parent, "failed to update interrupt mask: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mutex_unlock(&gpio->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct irq_chip max77620_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "max77620-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .irq_mask = max77620_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .irq_unmask = max77620_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .irq_set_type = max77620_gpio_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .irq_bus_lock = max77620_gpio_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct max77620_gpio *mgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MAX77620_CNFG_GPIO_DIR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MAX77620_CNFG_GPIO_DIR_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct max77620_gpio *mgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (val & MAX77620_CNFG_GPIO_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct max77620_gpio *mgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MAX77620_CNFG_GPIO_DIR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MAX77620_CNFG_GPIO_DIR_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) switch (debounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val = MAX77620_CNFG_GPIO_DBNC_None;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case 1 ... 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) val = MAX77620_CNFG_GPIO_DBNC_8ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case 8001 ... 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val = MAX77620_CNFG_GPIO_DBNC_16ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case 16001 ... 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = MAX77620_CNFG_GPIO_DBNC_32ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(mgpio->dev, "Illegal value %u\n", debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MAX77620_CNFG_GPIO_DBNC_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct max77620_gpio *mgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct max77620_gpio *mgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MAX77620_CNFG_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MAX77620_CNFG_GPIO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MAX77620_CNFG_GPIO_DRV_PUSHPULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case PIN_CONFIG_INPUT_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return max77620_gpio_set_debounce(mgpio, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pinconf_to_config_argument(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct max77620_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * GPIO interrupts may be left ON after bootloader, hence let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * pre-initialize hardware to the expected state by disabling all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * the interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for (i = 0; i < MAX77620_GPIO_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MAX77620_CNFG_GPIO_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(gpio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "failed to disable interrupt: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int max77620_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct max77620_gpio *mgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) gpio_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!mgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mutex_init(&mgpio->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mgpio->rmap = chip->rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mgpio->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mgpio->gpio_chip.label = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mgpio->gpio_chip.parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mgpio->gpio_chip.get = max77620_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mgpio->gpio_chip.set = max77620_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mgpio->gpio_chip.set_config = max77620_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mgpio->gpio_chip.can_sleep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mgpio->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) girq = &mgpio->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) girq->chip = &max77620_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) girq->init_hw = max77620_gpio_irq_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) platform_set_drvdata(pdev, mgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) max77620_gpio_irqhandler, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "max77620-gpio", mgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct platform_device_id max77620_gpio_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .name = "max77620-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { .name = "max20024-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct platform_driver max77620_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .driver.name = "max77620-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .probe = max77620_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .id_table = max77620_gpio_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_platform_driver(max77620_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_ALIAS("platform:max77620-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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