Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  MAX732x I2C Port Expander with 8/16 I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2007 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2008 Jack Ren <jack.ren@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2008 Eric Miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Derived from drivers/gpio/pca953x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_data/max732x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Each port of MAX732x (including MAX7319) falls into one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * following three types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *   - Push Pull Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *   - Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *   - Open Drain I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * designated by 'O', 'I' and 'P' individually according to MAXIM's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * datasheets. 'I' and 'P' ports are interrupt capables, some with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * a dedicated interrupt mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * There are two groups of I/O ports, each group usually includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * up to 8 I/O ports, and is accessed by a specific I2C address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *   - Group A : by I2C address 0b'110xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *   - Group B : by I2C address 0b'101xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * where 'xxxx' is decided by the connections of pin AD2/AD0.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * address used also affects the initial state of output signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * Within each group of ports, there are five known combinations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * I/O ports: 4I4O, 4P4O, 8I, 8P, 8O, see the definitions below for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * the detailed organization of these ports. Only Goup A is interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * capable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * GPIO numbers start from 'gpio_base + 0' to 'gpio_base + 8/16',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * and GPIOs from GROUP_A are numbered before those from GROUP_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * (if there are two groups).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * NOTE: MAX7328/MAX7329 are drop-in replacements for PCF8574/a, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * they are not supported by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PORT_NONE	0x0	/* '/' No Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PORT_OUTPUT	0x1	/* 'O' Push-Pull, Output Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PORT_INPUT	0x2	/* 'I' Input Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PORT_OPENDRAIN	0x3	/* 'P' Open-Drain, I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IO_4I4O		0x5AA5	/* O7 O6 I5 I4 I3 I2 O1 O0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IO_4P4O		0x5FF5	/* O7 O6 P5 P4 P3 P2 O1 O0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IO_8I		0xAAAA	/* I7 I6 I5 I4 I3 I2 I1 I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IO_8P		0xFFFF	/* P7 P6 P5 P4 P3 P2 P1 P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IO_8O		0x5555	/* O7 O6 O5 O4 O3 O2 O1 O0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define GROUP_A(x)	((x) & 0xffff)	/* I2C Addr: 0b'110xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define GROUP_B(x)	((x) << 16)	/* I2C Addr: 0b'101xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define INT_NONE	0x0	/* No interrupt capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define INT_NO_MASK	0x1	/* Has interrupts, no mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define INT_INDEP_MASK	0x2	/* Has interrupts, independent mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define INT_MERGED_MASK 0x3	/* Has interrupts, merged mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define INT_CAPS(x)	(((uint64_t)(x)) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	MAX7319,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	MAX7320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MAX7321,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	MAX7322,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MAX7323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MAX7324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MAX7325,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MAX7326,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MAX7327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static uint64_t max732x_features[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[MAX7319] = GROUP_A(IO_8I) | INT_CAPS(INT_MERGED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	[MAX7320] = GROUP_B(IO_8O),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[MAX7321] = GROUP_A(IO_8P) | INT_CAPS(INT_NO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[MAX7322] = GROUP_A(IO_4I4O) | INT_CAPS(INT_MERGED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[MAX7323] = GROUP_A(IO_4P4O) | INT_CAPS(INT_INDEP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[MAX7324] = GROUP_A(IO_8I) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[MAX7325] = GROUP_A(IO_8P) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	[MAX7326] = GROUP_A(IO_4I4O) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[MAX7327] = GROUP_A(IO_4P4O) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct i2c_device_id max732x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ "max7319", MAX7319 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ "max7320", MAX7320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ "max7321", MAX7321 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ "max7322", MAX7322 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ "max7323", MAX7323 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ "max7324", MAX7324 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ "max7325", MAX7325 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ "max7326", MAX7326 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ "max7327", MAX7327 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_DEVICE_TABLE(i2c, max732x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct of_device_id max732x_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ .compatible = "maxim,max7319" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ .compatible = "maxim,max7320" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ .compatible = "maxim,max7321" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ .compatible = "maxim,max7322" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ .compatible = "maxim,max7323" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ .compatible = "maxim,max7324" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ .compatible = "maxim,max7325" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ .compatible = "maxim,max7326" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .compatible = "maxim,max7327" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MODULE_DEVICE_TABLE(of, max732x_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct max732x_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct i2c_client *client;	/* "main" client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct i2c_client *client_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct i2c_client *client_group_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct i2c_client *client_group_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned int	mask_group_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int	dir_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned int	dir_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct mutex	lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	uint8_t		reg_out[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_GPIO_MAX732X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct mutex		irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	uint8_t			irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	uint8_t			irq_mask_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	uint8_t			irq_trig_raise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	uint8_t			irq_trig_fall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	uint8_t			irq_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	client = group_a ? chip->client_group_a : chip->client_group_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ret = i2c_smbus_write_byte(client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		dev_err(&client->dev, "failed writing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	client = group_a ? chip->client_group_a : chip->client_group_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ret = i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(&client->dev, "failed reading\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	*val = (uint8_t)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline int is_group_a(struct max732x_chip *chip, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return (1u << off) & chip->mask_group_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int max732x_gpio_get_value(struct gpio_chip *gc, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	uint8_t reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ret = max732x_readb(chip, is_group_a(chip, off), &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return !!(reg_val & (1u << (off & 0x7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void max732x_gpio_set_mask(struct gpio_chip *gc, unsigned off, int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				  int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	uint8_t reg_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	reg_out = (reg_out & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ret = max732x_writeb(chip, is_group_a(chip, off), reg_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* update the shadow register then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (off > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		chip->reg_out[1] = reg_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		chip->reg_out[0] = reg_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	unsigned base = off & ~0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	uint8_t mask = 1u << (off & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void max732x_gpio_set_multiple(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				      unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned mask_lo = mask[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	unsigned mask_hi = (mask[0] >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (mask_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		max732x_gpio_set_mask(gc, 0, mask_lo, bits[0] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (mask_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		max732x_gpio_set_mask(gc, 8, mask_hi, (bits[0] >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int max732x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	unsigned int mask = 1u << off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if ((mask & chip->dir_input) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev_dbg(&chip->client->dev, "%s port %d is output only\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			chip->client->name, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * Open-drain pins must be set to high impedance (which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * equivalent to output-high) to be turned into an input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if ((mask & chip->dir_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		max732x_gpio_set_value(gc, off, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int max732x_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		unsigned off, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned int mask = 1u << off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if ((mask & chip->dir_output) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		dev_dbg(&chip->client->dev, "%s port %d is input only\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			chip->client->name, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	max732x_gpio_set_value(gc, off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_GPIO_MAX732X_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int max732x_writew(struct max732x_chip *chip, uint16_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	val = cpu_to_le16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ret = i2c_master_send(chip->client_group_a, (char *)&val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		dev_err(&chip->client_group_a->dev, "failed writing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int max732x_readw(struct max732x_chip *chip, uint16_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ret = i2c_master_recv(chip->client_group_a, (char *)val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		dev_err(&chip->client_group_a->dev, "failed reading\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	*val = le16_to_cpu(*val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void max732x_irq_update_mask(struct max732x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	uint16_t msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (chip->irq_mask == chip->irq_mask_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	chip->irq_mask = chip->irq_mask_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (chip->irq_features == INT_NO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	switch (chip->irq_features) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	case INT_INDEP_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		msg = (chip->irq_mask << 8) | chip->reg_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		max732x_writew(chip, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	case INT_MERGED_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		msg = chip->irq_mask | chip->reg_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		max732x_writeb(chip, 1, (uint8_t)msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void max732x_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	chip->irq_mask_cur &= ~(1 << d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void max732x_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	chip->irq_mask_cur |= 1 << d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void max732x_irq_bus_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	mutex_lock(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	chip->irq_mask_cur = chip->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void max732x_irq_bus_sync_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	uint16_t new_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	uint16_t level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	max732x_irq_update_mask(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	while (new_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		level = __ffs(new_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		max732x_gpio_direction_input(&chip->gpio_chip, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		new_irqs &= ~(1 << level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	mutex_unlock(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int max732x_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct max732x_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	uint16_t off = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	uint16_t mask = 1 << off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (!(mask & chip->dir_input)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_dbg(&chip->client->dev, "%s port %d is output only\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			chip->client->name, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (!(type & IRQ_TYPE_EDGE_BOTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			d->irq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		chip->irq_trig_fall |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		chip->irq_trig_fall &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		chip->irq_trig_raise |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		chip->irq_trig_raise &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int max732x_irq_set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	struct max732x_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	irq_set_irq_wake(chip->client->irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct irq_chip max732x_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.name			= "max732x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.irq_mask		= max732x_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.irq_unmask		= max732x_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.irq_bus_lock		= max732x_irq_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.irq_bus_sync_unlock	= max732x_irq_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.irq_set_type		= max732x_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.irq_set_wake		= max732x_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static uint8_t max732x_irq_pending(struct max732x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	uint8_t cur_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	uint8_t old_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	uint8_t trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	uint8_t pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	uint16_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ret = max732x_readw(chip, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	trigger = status >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	trigger &= chip->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (!trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	cur_stat = status & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	cur_stat &= chip->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	old_stat = cur_stat ^ trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	pending = (old_stat & chip->irq_trig_fall) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		  (cur_stat & chip->irq_trig_raise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	pending &= trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static irqreturn_t max732x_irq_handler(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	struct max732x_chip *chip = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	uint8_t pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	uint8_t level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	pending = max732x_irq_pending(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		level = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 						   level));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		pending &= ~(1 << level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	} while (pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int max732x_irq_setup(struct max732x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 			     const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	struct max732x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	int has_irq = max732x_features[id->driver_data] >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	int irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (((pdata && pdata->irq_base) || client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 			&& has_irq != INT_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 			irq_base = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		chip->irq_features = has_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		mutex_init(&chip->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 				NULL, max732x_irq_handler, IRQF_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 				IRQF_TRIGGER_FALLING | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 				dev_name(&client->dev), chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 			dev_err(&client->dev, "failed to request irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 				client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		girq = &chip->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		girq->chip = &max732x_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		/* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		girq->first = irq_base; /* FIXME: get rid of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #else /* CONFIG_GPIO_MAX732X_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int max732x_irq_setup(struct max732x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 			     const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	struct max732x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	int has_irq = max732x_features[id->driver_data] >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	if (((pdata && pdata->irq_base) || client->irq) && has_irq != INT_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		dev_warn(&client->dev, "interrupt support not compiled in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int max732x_setup_gpio(struct max732x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 					const struct i2c_device_id *id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 					unsigned gpio_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	struct gpio_chip *gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	uint32_t id_data = (uint32_t)max732x_features[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	int i, port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	for (i = 0; i < 16; i++, id_data >>= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		unsigned int mask = 1 << port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		switch (id_data & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		case PORT_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 			chip->dir_output |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		case PORT_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 			chip->dir_input |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		case PORT_OPENDRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 			chip->dir_output |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 			chip->dir_input |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		if (i < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 			chip->mask_group_a |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	if (chip->dir_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		gc->direction_input = max732x_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (chip->dir_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		gc->direction_output = max732x_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		gc->set = max732x_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		gc->set_multiple = max732x_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	gc->get = max732x_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	gc->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	gc->base = gpio_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	gc->ngpio = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	gc->label = chip->client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	gc->parent = &chip->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct max732x_platform_data *of_gpio_max732x(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	struct max732x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	pdata->gpio_base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int max732x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 				   const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	struct max732x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	struct max732x_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	struct i2c_client *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	uint16_t addr_a, addr_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	int ret, nr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	if (!pdata && node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		pdata = of_gpio_max732x(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		dev_dbg(&client->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	chip->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	chip->gpio_chip.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	addr_a = (client->addr & 0x0f) | 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	addr_b = (client->addr & 0x0f) | 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	switch (client->addr & 0x70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		chip->client_group_a = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		if (nr_port > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 			c = devm_i2c_new_dummy_device(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 						      client->adapter, addr_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 			if (IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 				dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 					"Failed to allocate I2C device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 				return PTR_ERR(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 			chip->client_group_b = chip->client_dummy = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	case 0x50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 		chip->client_group_b = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 		if (nr_port > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 			c = devm_i2c_new_dummy_device(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 						      client->adapter, addr_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 			if (IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 				dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 					"Failed to allocate I2C device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 				return PTR_ERR(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 			chip->client_group_a = chip->client_dummy = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 		dev_err(&client->dev, "invalid I2C address specified %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 				client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	if (nr_port > 8 && !chip->client_dummy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 			"Failed to allocate second group I2C device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	if (nr_port > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 		ret = max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	ret = max732x_irq_setup(chip, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	if (pdata->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 		ret = pdata->setup(client, chip->gpio_chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 				chip->gpio_chip.ngpio, pdata->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 			dev_warn(&client->dev, "setup failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	i2c_set_clientdata(client, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int max732x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	struct max732x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	struct max732x_chip *chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 	if (pdata && pdata->teardown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 		ret = pdata->teardown(client, chip->gpio_chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 				chip->gpio_chip.ngpio, pdata->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 			dev_err(&client->dev, "%s failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 					"teardown", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct i2c_driver max732x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 		.name		= "max732x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 		.of_match_table	= of_match_ptr(max732x_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 	.probe		= max732x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	.remove		= max732x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	.id_table	= max732x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int __init max732x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	return i2c_add_driver(&max732x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* register after i2c postcore initcall and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)  * subsys initcalls that may rely on these GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) subsys_initcall(max732x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void __exit max732x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	i2c_del_driver(&max732x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) module_exit(max732x_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_DESCRIPTION("GPIO expander driver for MAX732X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MODULE_LICENSE("GPL");