^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gpio-max3191x.c - GPIO driver for Maxim MAX3191x industrial serializer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 KUNBUS GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The MAX3191x makes 8 digital 24V inputs available via SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Multiple chips can be daisy-chained, the spec does not impose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a limit on the number of chips and neither does this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Either of two modes is selectable: In 8-bit mode, only the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of the inputs is clocked out to achieve high readout speeds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * In 16-bit mode, an additional status byte is clocked out with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * a CRC and indicator bits for undervoltage and overtemperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The driver returns an error instead of potentially bogus data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * if any of these fault conditions occur. However it does allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * readout of non-faulting chips in the same daisy-chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * MAX3191x supports four debounce settings and the driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * capable of configuring these differently for each chip in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * daisy-chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * If the chips are hardwired to 8-bit mode ("modesel" pulled high),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * gpio-pisosr.c can be used alternatively to this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * https://datasheets.maximintegrated.com/en/ds/MAX31910.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * https://datasheets.maximintegrated.com/en/ds/MAX31911.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * https://datasheets.maximintegrated.com/en/ds/MAX31912.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * https://datasheets.maximintegrated.com/en/ds/MAX31913.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * https://datasheets.maximintegrated.com/en/ds/MAX31953-MAX31963.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/crc8.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum max3191x_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) STATUS_BYTE_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) STATUS_BYTE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct max3191x_chip - max3191x daisy-chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @gpio: GPIO controller struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @lock: protects read sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @nchips: number of chips in the daisy-chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @mode: current mode, 0 for 16-bit, 1 for 8-bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * for simplicity, all chips in the daisy-chain are assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * to use the same mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @modesel_pins: GPIO pins to configure modesel of each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @fault_pins: GPIO pins to detect fault of each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @db0_pins: GPIO pins to configure debounce of each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @db1_pins: GPIO pins to configure debounce of each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @mesg: SPI message to perform a readout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @xfer: SPI transfer used by @mesg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @crc_error: bitmap signaling CRC error for each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @overtemp: bitmap signaling overtemperature alarm for each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @undervolt1: bitmap signaling undervoltage alarm for each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @undervolt2: bitmap signaling undervoltage warning for each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @fault: bitmap signaling assertion of @fault_pins for each chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @ignore_uv: whether to ignore undervoltage alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * set by a device property if the chips are powered through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 5VOUT instead of VCC24V, in which case they will constantly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * signal undervoltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * for simplicity, all chips in the daisy-chain are assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * to be powered the same way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct max3191x_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 nchips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum max3191x_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct gpio_descs *modesel_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gpio_descs *fault_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct gpio_descs *db0_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct gpio_descs *db1_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spi_message mesg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct spi_transfer xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long *crc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long *overtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long *undervolt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long *undervolt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long *fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bool ignore_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX3191X_NGPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAX3191X_CRC8_POLYNOMIAL 0xa8 /* (x^5) + x^4 + x^2 + x^0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DECLARE_CRC8_TABLE(max3191x_crc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int max3191x_get_direction(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return GPIO_LINE_DIRECTION_IN; /* always in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int max3191x_direction_input(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int max3191x_direction_output(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void max3191x_set(struct gpio_chip *gpio, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void max3191x_set_multiple(struct gpio_chip *gpio, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int max3191x_wordlen(struct max3191x_chip *max3191x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return max3191x->mode == STATUS_BYTE_ENABLED ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int max3191x_readout_locked(struct max3191x_chip *max3191x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device *dev = max3191x->gpio.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int val, i, ot = 0, uv1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) val = spi_sync(spi, &max3191x->mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err_ratelimited(dev, "SPI receive error %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 0; i < max3191x->nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (max3191x->mode == STATUS_BYTE_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 in = ((u8 *)max3191x->xfer.rx_buf)[i * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 status = ((u8 *)max3191x->xfer.rx_buf)[i * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = (status & 0xf8) != crc8(max3191x_crc8, &in, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __assign_bit(i, max3191x->crc_error, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "chip %d: CRC error\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ot = (status >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __assign_bit(i, max3191x->overtemp, ot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "chip %d: overtemperature\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!max3191x->ignore_uv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uv1 = !((status >> 2) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __assign_bit(i, max3191x->undervolt1, uv1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (uv1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "chip %d: undervoltage\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = !(status & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __assign_bit(i, max3191x->undervolt2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (val && !uv1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_warn_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "chip %d: voltage warn\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (max3191x->fault_pins && !max3191x->ignore_uv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* fault pin shared by all chips or per chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct gpio_desc *fault_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (max3191x->fault_pins->ndescs == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ? max3191x->fault_pins->desc[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) : max3191x->fault_pins->desc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = gpiod_get_value_cansleep(fault_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "GPIO read error %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __assign_bit(i, max3191x->fault, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (val && !uv1 && !ot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "chip %d: fault\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static bool max3191x_chip_is_faulting(struct max3191x_chip *max3191x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int chipnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* without status byte the only diagnostic is the fault pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!max3191x->ignore_uv && test_bit(chipnum, max3191x->fault))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (max3191x->mode == STATUS_BYTE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return test_bit(chipnum, max3191x->crc_error) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) test_bit(chipnum, max3191x->overtemp) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) (!max3191x->ignore_uv &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) test_bit(chipnum, max3191x->undervolt1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int max3191x_get(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret, chipnum, wordlen = max3191x_wordlen(max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mutex_lock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = max3191x_readout_locked(max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) chipnum = offset / MAX3191X_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (max3191x_chip_is_faulting(max3191x, chipnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = (in >> (offset % MAX3191X_NGPIO)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mutex_unlock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const unsigned int wordlen = max3191x_wordlen(max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mutex_lock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = max3191x_readout_locked(max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bitmap_zero(bits, gpio->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for_each_set_clump8(bit, gpio_mask, mask, gpio->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int chipnum = bit / MAX3191X_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (max3191x_chip_is_faulting(max3191x, chipnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) in &= gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bitmap_set_value8(bits, in, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mutex_unlock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int max3191x_set_config(struct gpio_chip *gpio, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 debounce, chipnum, db0_val, db1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!max3191x->db0_pins || !max3191x->db1_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (debounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) db0_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) db1_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 1 ... 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) db0_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) db1_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 26 ... 750:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) db0_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) db1_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 751 ... 3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) db0_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) db1_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (max3191x->db0_pins->ndescs == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) chipnum = 0; /* all chips use the same pair of debounce pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) chipnum = offset / MAX3191X_NGPIO; /* per chip debounce pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mutex_lock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) gpiod_set_value_cansleep(max3191x->db0_pins->desc[chipnum], db0_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) gpiod_set_value_cansleep(max3191x->db1_pins->desc[chipnum], db1_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mutex_unlock(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void gpiod_set_array_single_value_cansleep(unsigned int ndescs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct gpio_desc **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct gpio_array *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) values = bitmap_alloc(ndescs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bitmap_fill(values, ndescs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bitmap_zero(values, ndescs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gpiod_set_array_value_cansleep(ndescs, desc, info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) kfree(values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct gpio_descs *devm_gpiod_get_array_optional_count(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct device *dev, const char *con_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) enum gpiod_flags flags, unsigned int expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct gpio_descs *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int found = gpiod_count(dev, con_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (found == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (found != expected && found != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev, "ignoring %s-gpios: found %d, expected %u or 1\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) con_id, found, expected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) descs = devm_gpiod_get_array_optional(dev, con_id, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ERR(descs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(dev, "failed to get %s-gpios: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) con_id, PTR_ERR(descs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int max3191x_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct max3191x_chip *max3191x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int n, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) max3191x = devm_kzalloc(dev, sizeof(*max3191x), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!max3191x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spi_set_drvdata(spi, max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) max3191x->nchips = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) device_property_read_u32(dev, "#daisy-chained-devices",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) n = BITS_TO_LONGS(max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) max3191x->crc_error = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) max3191x->undervolt1 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) max3191x->undervolt2 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) max3191x->overtemp = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) max3191x->fault = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) max3191x->xfer.rx_buf = devm_kcalloc(dev, max3191x->nchips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 2, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!max3191x->crc_error || !max3191x->undervolt1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) !max3191x->overtemp || !max3191x->undervolt2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) !max3191x->fault || !max3191x->xfer.rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) max3191x->modesel_pins = devm_gpiod_get_array_optional_count(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "maxim,modesel", GPIOD_ASIS, max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) max3191x->fault_pins = devm_gpiod_get_array_optional_count(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "maxim,fault", GPIOD_IN, max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) max3191x->db0_pins = devm_gpiod_get_array_optional_count(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "maxim,db0", GPIOD_OUT_LOW, max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) max3191x->db1_pins = devm_gpiod_get_array_optional_count(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "maxim,db1", GPIOD_OUT_LOW, max3191x->nchips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) max3191x->mode = device_property_read_bool(dev, "maxim,modesel-8bit")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ? STATUS_BYTE_DISABLED : STATUS_BYTE_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (max3191x->modesel_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) gpiod_set_array_single_value_cansleep(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) max3191x->modesel_pins->ndescs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) max3191x->modesel_pins->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) max3191x->modesel_pins->info, max3191x->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) max3191x->ignore_uv = device_property_read_bool(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "maxim,ignore-undervoltage");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (max3191x->db0_pins && max3191x->db1_pins &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) max3191x->db0_pins->ndescs != max3191x->db1_pins->ndescs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(dev, "ignoring maxim,db*-gpios: array len mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) devm_gpiod_put_array(dev, max3191x->db0_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) devm_gpiod_put_array(dev, max3191x->db1_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) max3191x->db0_pins = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) max3191x->db1_pins = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) max3191x->xfer.len = max3191x->nchips * max3191x_wordlen(max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spi_message_init_with_transfers(&max3191x->mesg, &max3191x->xfer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) max3191x->gpio.label = spi->modalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) max3191x->gpio.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) max3191x->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) max3191x->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) max3191x->gpio.ngpio = max3191x->nchips * MAX3191X_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) max3191x->gpio.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) max3191x->gpio.get_direction = max3191x_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) max3191x->gpio.direction_input = max3191x_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) max3191x->gpio.direction_output = max3191x_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) max3191x->gpio.set = max3191x_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) max3191x->gpio.set_multiple = max3191x_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) max3191x->gpio.get = max3191x_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) max3191x->gpio.get_multiple = max3191x_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) max3191x->gpio.set_config = max3191x_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_init(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = gpiochip_add_data(&max3191x->gpio, max3191x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mutex_destroy(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int max3191x_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct max3191x_chip *max3191x = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) gpiochip_remove(&max3191x->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mutex_destroy(&max3191x->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int __init max3191x_register_driver(struct spi_driver *sdrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) crc8_populate_msb(max3191x_crc8, MAX3191X_CRC8_POLYNOMIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return spi_register_driver(sdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct of_device_id max3191x_of_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .compatible = "maxim,max31910" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { .compatible = "maxim,max31911" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .compatible = "maxim,max31912" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .compatible = "maxim,max31913" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .compatible = "maxim,max31953" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .compatible = "maxim,max31963" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DEVICE_TABLE(of, max3191x_of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct spi_device_id max3191x_spi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { "max31910" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { "max31911" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { "max31912" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { "max31913" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { "max31953" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { "max31963" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DEVICE_TABLE(spi, max3191x_spi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct spi_driver max3191x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "max3191x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .of_match_table = of_match_ptr(max3191x_of_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .probe = max3191x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .remove = max3191x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .id_table = max3191x_spi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) module_driver(max3191x_driver, max3191x_register_driver, spi_unregister_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_AUTHOR("Lukas Wunner <lukas@wunner.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_DESCRIPTION("GPIO driver for Maxim MAX3191x industrial serializer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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