Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * GPIO driver for LPC32xx SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Kevin Wells <kevin.wells@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LPC32XX_GPIO_P3_INP_STATE		(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LPC32XX_GPIO_P3_OUTP_SET		(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LPC32XX_GPIO_P3_OUTP_CLR		(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LPC32XX_GPIO_P3_OUTP_STATE		(0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LPC32XX_GPIO_P2_DIR_SET			(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LPC32XX_GPIO_P2_DIR_CLR			(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LPC32XX_GPIO_P2_DIR_STATE		(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LPC32XX_GPIO_P2_INP_STATE		(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LPC32XX_GPIO_P2_OUTP_SET		(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPC32XX_GPIO_P2_OUTP_CLR		(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPC32XX_GPIO_P2_MUX_SET			(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC32XX_GPIO_P2_MUX_CLR			(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LPC32XX_GPIO_P2_MUX_STATE		(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LPC32XX_GPIO_P0_INP_STATE		(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LPC32XX_GPIO_P0_OUTP_SET		(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LPC32XX_GPIO_P0_OUTP_CLR		(0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LPC32XX_GPIO_P0_OUTP_STATE		(0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LPC32XX_GPIO_P0_DIR_SET			(0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LPC32XX_GPIO_P0_DIR_CLR			(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LPC32XX_GPIO_P0_DIR_STATE		(0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LPC32XX_GPIO_P1_INP_STATE		(0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LPC32XX_GPIO_P1_OUTP_SET		(0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LPC32XX_GPIO_P1_OUTP_CLR		(0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define LPC32XX_GPIO_P1_OUTP_STATE		(0x06C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LPC32XX_GPIO_P1_DIR_SET			(0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LPC32XX_GPIO_P1_DIR_CLR			(0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LPC32XX_GPIO_P1_DIR_STATE		(0x078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GPIO012_PIN_TO_BIT(x)			(1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GPIO3_PIN_TO_BIT(x)			(1 << ((x) + 25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GPO3_PIN_TO_BIT(x)			(1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GPO3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define LPC32XX_GPIO_P0_MAX	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define LPC32XX_GPIO_P1_MAX	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LPC32XX_GPIO_P2_MAX	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LPC32XX_GPIO_P3_MAX	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LPC32XX_GPI_P3_MAX	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define LPC32XX_GPO_P3_MAX	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define LPC32XX_GPIO_P0_GRP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define LPC32XX_GPIO_P1_GRP	(LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define LPC32XX_GPIO_P2_GRP	(LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define LPC32XX_GPIO_P3_GRP	(LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define LPC32XX_GPI_P3_GRP	(LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define LPC32XX_GPO_P3_GRP	(LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long inp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned long outp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned long outp_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned long outp_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned long dir_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned long dir_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * GPIO names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	"p0.0", "p0.1", "p0.2", "p0.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	"p0.4", "p0.5", "p0.6", "p0.7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	"p1.0", "p1.1", "p1.2", "p1.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	"p1.4", "p1.5", "p1.6", "p1.7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	"p1.8", "p1.9", "p1.10", "p1.11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	"p1.12", "p1.13", "p1.14", "p1.15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	"p1.16", "p1.17", "p1.18", "p1.19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	"p1.20", "p1.21", "p1.22", "p1.23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	"p2.0", "p2.1", "p2.2", "p2.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	"p2.4", "p2.5", "p2.6", "p2.7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	"p2.8", "p2.9", "p2.10", "p2.11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	"p2.12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	"gpio00", "gpio01", "gpio02", "gpio03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	"gpio04", "gpio05"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	"gpi00", "gpi01", "gpi02", "gpi03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	"gpi04", "gpi05", "gpi06", "gpi07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	"gpi08", "gpi09",  NULL,    NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 NULL,    NULL,    NULL,   "gpi15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	"gpi16", "gpi17", "gpi18", "gpi19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	"gpi20", "gpi21", "gpi22", "gpi23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	"gpi24", "gpi25", "gpi26", "gpi27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	"gpi28"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	"gpo00", "gpo01", "gpo02", "gpo03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	"gpo04", "gpo05", "gpo06", "gpo07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	"gpo08", "gpo09", "gpo10", "gpo11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	"gpo12", "gpo13", "gpo14", "gpo15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	"gpo16", "gpo17", "gpo18", "gpo19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	"gpo20", "gpo21", "gpo22", "gpo23"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct gpio_regs gpio_grp_regs_p0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.inp_state	= LPC32XX_GPIO_P0_INP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.outp_set	= LPC32XX_GPIO_P0_OUTP_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.outp_clr	= LPC32XX_GPIO_P0_OUTP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.dir_set	= LPC32XX_GPIO_P0_DIR_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.dir_clr	= LPC32XX_GPIO_P0_DIR_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct gpio_regs gpio_grp_regs_p1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.inp_state	= LPC32XX_GPIO_P1_INP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.outp_set	= LPC32XX_GPIO_P1_OUTP_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.outp_clr	= LPC32XX_GPIO_P1_OUTP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.dir_set	= LPC32XX_GPIO_P1_DIR_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.dir_clr	= LPC32XX_GPIO_P1_DIR_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct gpio_regs gpio_grp_regs_p2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.inp_state	= LPC32XX_GPIO_P2_INP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.outp_set	= LPC32XX_GPIO_P2_OUTP_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.outp_clr	= LPC32XX_GPIO_P2_OUTP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct gpio_regs gpio_grp_regs_p3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.inp_state	= LPC32XX_GPIO_P3_INP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.outp_state	= LPC32XX_GPIO_P3_OUTP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.outp_set	= LPC32XX_GPIO_P3_OUTP_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct lpc32xx_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct gpio_chip	chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct gpio_regs	*gpio_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	void __iomem		*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return __raw_readl(group->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	__raw_writel(val, group->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned pin, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			group->gpio_grp->dir_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			group->gpio_grp->dir_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned pin, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 u = GPIO3_PIN_TO_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		gpreg_write(group, u, group->gpio_grp->dir_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		gpreg_write(group, u, group->gpio_grp->dir_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned pin, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			group->gpio_grp->outp_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			group->gpio_grp->outp_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned pin, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 u = GPIO3_PIN_TO_BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		gpreg_write(group, u, group->gpio_grp->outp_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		gpreg_write(group, u, group->gpio_grp->outp_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned pin, int high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int state = gpreg_read(group, group->gpio_grp->inp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return GPIO3_PIN_IN_SEL(state, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * GPIO primitives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	__set_gpio_dir_p012(group, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	__set_gpio_dir_p3(group, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return !!__get_gpio_state_p012(group, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return !!__get_gpio_state_p3(group, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return !!__get_gpi_state_p3(group, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	__set_gpio_level_p012(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	__set_gpio_dir_p012(group, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	__set_gpio_level_p3(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	__set_gpio_dir_p3(group, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	__set_gpo_level_p3(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	__set_gpio_level_p012(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	__set_gpio_level_p3(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	__set_gpo_level_p3(group, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return !!__get_gpo_state_p3(group, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (pin < chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			.label			= "gpio_p0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			.direction_input	= lpc32xx_gpio_dir_input_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			.get			= lpc32xx_gpio_get_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			.direction_output	= lpc32xx_gpio_dir_output_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			.set			= lpc32xx_gpio_set_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			.to_irq			= lpc32xx_gpio_to_irq_p01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			.base			= LPC32XX_GPIO_P0_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			.ngpio			= LPC32XX_GPIO_P0_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			.names			= gpio_p0_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.gpio_grp = &gpio_grp_regs_p0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			.label			= "gpio_p1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			.direction_input	= lpc32xx_gpio_dir_input_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			.get			= lpc32xx_gpio_get_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			.direction_output	= lpc32xx_gpio_dir_output_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			.set			= lpc32xx_gpio_set_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			.to_irq			= lpc32xx_gpio_to_irq_p01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			.base			= LPC32XX_GPIO_P1_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 			.ngpio			= LPC32XX_GPIO_P1_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			.names			= gpio_p1_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.gpio_grp = &gpio_grp_regs_p1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			.label			= "gpio_p2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			.direction_input	= lpc32xx_gpio_dir_input_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			.get			= lpc32xx_gpio_get_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			.direction_output	= lpc32xx_gpio_dir_output_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			.set			= lpc32xx_gpio_set_value_p012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			.base			= LPC32XX_GPIO_P2_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			.ngpio			= LPC32XX_GPIO_P2_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			.names			= gpio_p2_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.gpio_grp = &gpio_grp_regs_p2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			.label			= "gpio_p3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			.direction_input	= lpc32xx_gpio_dir_input_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			.get			= lpc32xx_gpio_get_value_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			.direction_output	= lpc32xx_gpio_dir_output_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			.set			= lpc32xx_gpio_set_value_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			.to_irq			= lpc32xx_gpio_to_irq_gpio_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			.base			= LPC32XX_GPIO_P3_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			.ngpio			= LPC32XX_GPIO_P3_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			.names			= gpio_p3_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		.gpio_grp = &gpio_grp_regs_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			.label			= "gpi_p3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			.direction_input	= lpc32xx_gpio_dir_in_always,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			.get			= lpc32xx_gpi_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			.to_irq			= lpc32xx_gpio_to_irq_gpi_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			.base			= LPC32XX_GPI_P3_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 			.ngpio			= LPC32XX_GPI_P3_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			.names			= gpi_p3_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.gpio_grp = &gpio_grp_regs_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			.label			= "gpo_p3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			.direction_output	= lpc32xx_gpio_dir_out_always,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 			.set			= lpc32xx_gpo_set_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			.get			= lpc32xx_gpo_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			.request		= lpc32xx_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 			.base			= LPC32XX_GPO_P3_GRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 			.ngpio			= LPC32XX_GPO_P3_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 			.names			= gpo_p3_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			.can_sleep		= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		.gpio_grp = &gpio_grp_regs_p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int lpc32xx_of_xlate(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 			    const struct of_phandle_args *gpiospec, u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	/* Is this the correct bank? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	u32 bank = gpiospec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	    (gc != &lpc32xx_gpiochip[bank].chip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		*flags = gpiospec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	return gpiospec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int lpc32xx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 			lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 			lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 			lpc32xx_gpiochip[i].reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 				  &lpc32xx_gpiochip[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct of_device_id lpc32xx_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	{ .compatible = "nxp,lpc3220-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct platform_driver lpc32xx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		.name	= "lpc32xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	.probe		= lpc32xx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) module_platform_driver(lpc32xx_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");