Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * GPIO driver for NXP LPC18xx/43xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Vladimir Zapolskiy <vz@mleia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* LPC18xx GPIO register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LPC18XX_REG_DIR(n)	(0x2000 + n * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LPC18XX_MAX_PORTS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LPC18XX_PINS_PER_PORT	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* LPC18xx GPIO pin interrupt controller register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPC18XX_GPIO_PIN_IC_ISEL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC18XX_GPIO_PIN_IC_IENR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LPC18XX_GPIO_PIN_IC_SIENR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LPC18XX_GPIO_PIN_IC_CIENR	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LPC18XX_GPIO_PIN_IC_IENF	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LPC18XX_GPIO_PIN_IC_SIENF	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LPC18XX_GPIO_PIN_IC_CIENF	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LPC18XX_GPIO_PIN_IC_RISE	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LPC18XX_GPIO_PIN_IC_FALL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LPC18XX_GPIO_PIN_IC_IST		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define NR_LPC18XX_GPIO_PIN_IC_IRQS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct lpc18xx_gpio_pin_ic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct raw_spinlock lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct lpc18xx_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct lpc18xx_gpio_pin_ic *pin_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					    u32 pin, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		val &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		val |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					   u32 pin, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writel_relaxed(BIT(pin), ic->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	raw_spin_lock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					LPC18XX_GPIO_PIN_IC_CIENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					LPC18XX_GPIO_PIN_IC_CIENF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	raw_spin_unlock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	raw_spin_lock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 					LPC18XX_GPIO_PIN_IC_SIENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 					LPC18XX_GPIO_PIN_IC_SIENF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	raw_spin_unlock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	raw_spin_lock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 					LPC18XX_GPIO_PIN_IC_IST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	raw_spin_unlock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	raw_spin_lock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (type & IRQ_TYPE_LEVEL_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 					LPC18XX_GPIO_PIN_IC_SIENF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	} else if (type & IRQ_TYPE_LEVEL_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					LPC18XX_GPIO_PIN_IC_CIENF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	raw_spin_unlock(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct irq_chip lpc18xx_gpio_pin_ic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.name		= "LPC18xx GPIO pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.irq_mask	= lpc18xx_gpio_pin_ic_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.irq_unmask	= lpc18xx_gpio_pin_ic_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.irq_eoi	= lpc18xx_gpio_pin_ic_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.irq_set_type	= lpc18xx_gpio_pin_ic_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.flags		= IRQCHIP_SET_TYPE_MASKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					    unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 					    unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct irq_fwspec parent_fwspec, *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct lpc18xx_gpio_pin_ic *ic = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (nr_irqs != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	parent_fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	parent_fwspec.param[0] = hwirq + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		pr_err("failed to allocate parent irq %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		       parent_fwspec.param[0], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 					     &lpc18xx_gpio_pin_ic, ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.alloc	= lpc18xx_gpio_pin_ic_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.xlate	= irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.free	= irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct device *dev = gc->gpio.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct device_node *parent_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct lpc18xx_gpio_pin_ic *ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int ret, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	parent_node = of_irq_find_parent(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (!parent_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	parent_domain = irq_find_host(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	of_node_put(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (!ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	index = of_property_match_string(dev->of_node, "reg-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					 "gpio-pin-ic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto free_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ret = of_address_to_resource(dev->of_node, index, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto free_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ic->base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (IS_ERR(ic->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = PTR_ERR(ic->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		goto free_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	raw_spin_lock_init(&ic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ic->domain = irq_domain_add_hierarchy(parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					      NR_LPC18XX_GPIO_PIN_IC_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					      dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					      &lpc18xx_gpio_pin_ic_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 					      ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!ic->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		pr_err("unable to add irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		goto free_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	gc->pin_ic = ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) free_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	devm_iounmap(dev, ic->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) free_ic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	devm_kfree(dev, ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	writeb(value ? 1 : 0, gc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int lpc18xx_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return !!readb(gc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int lpc18xx_gpio_direction(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				  bool out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	u32 port, pin, dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	port = offset / LPC18XX_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	pin  = offset % LPC18XX_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	spin_lock_irqsave(&gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	dir = readl(gc->base + LPC18XX_REG_DIR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dir |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dir &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	writel(dir, gc->base + LPC18XX_REG_DIR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	spin_unlock_irqrestore(&gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int lpc18xx_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return lpc18xx_gpio_direction(chip, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int lpc18xx_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					 unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	lpc18xx_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return lpc18xx_gpio_direction(chip, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct gpio_chip lpc18xx_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.label			= "lpc18xx/43xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.request		= gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.free			= gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.direction_input	= lpc18xx_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.direction_output	= lpc18xx_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.set			= lpc18xx_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.get			= lpc18xx_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.ngpio			= LPC18XX_MAX_PORTS * LPC18XX_PINS_PER_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int lpc18xx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct lpc18xx_gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int index, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	gc->gpio = lpc18xx_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	platform_set_drvdata(pdev, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	index = of_property_match_string(dev->of_node, "reg-names", "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		/* To support backward compatibility take the first resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		gc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		ret = of_address_to_resource(dev->of_node, index, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		gc->base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (IS_ERR(gc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return PTR_ERR(gc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	gc->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (IS_ERR(gc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		dev_err(dev, "input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return PTR_ERR(gc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ret = clk_prepare_enable(gc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		dev_err(dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	spin_lock_init(&gc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	gc->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ret = devm_gpiochip_add_data(dev, &gc->gpio, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		dev_err(dev, "failed to add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		clk_disable_unprepare(gc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* On error GPIO pin interrupt controller just won't be registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	lpc18xx_gpio_pin_ic_probe(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int lpc18xx_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (gc->pin_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		irq_domain_remove(gc->pin_ic->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	clk_disable_unprepare(gc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct of_device_id lpc18xx_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{ .compatible = "nxp,lpc1850-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_DEVICE_TABLE(of, lpc18xx_gpio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct platform_driver lpc18xx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.probe	= lpc18xx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.remove	= lpc18xx_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.name		= "lpc18xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.of_match_table	= lpc18xx_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) module_platform_driver(lpc18xx_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_AUTHOR("Vladimir Zapolskiy <vz@mleia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_LICENSE("GPL v2");