^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Janz MODULbus VMOD-TTL GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/janz.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRV_NAME "janz-ttl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORTA_DIRECTION 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PORTB_DIRECTION 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PORTC_DIRECTION 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PORTA_IOCTL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PORTB_IOCTL 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORTC_IOCTL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MASTER_INT_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MASTER_CONF_CTL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CONF_PAE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CONF_PBE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CONF_PCE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ttl_control_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __be16 portc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __be16 portb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __be16 porta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __be16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ttl_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* base address of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct ttl_control_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 portc_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 portb_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 porta_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int ttl_get_value(struct gpio_chip *gpio, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ttl_module *mod = dev_get_drvdata(gpio->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 *shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (offset < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) shadow = &mod->porta_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } else if (offset < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) shadow = &mod->portb_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) offset -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) shadow = &mod->portc_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_lock(&mod->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = *shadow & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) spin_unlock(&mod->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return !!ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void ttl_set_value(struct gpio_chip *gpio, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ttl_module *mod = dev_get_drvdata(gpio->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 *shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (offset < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) port = &mod->regs->porta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) shadow = &mod->porta_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else if (offset < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) port = &mod->regs->portb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) shadow = &mod->portb_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) offset -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) port = &mod->regs->portc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) shadow = &mod->portc_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock(&mod->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *shadow |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *shadow &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) iowrite16be(*shadow, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spin_unlock(&mod->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iowrite16be(reg, &mod->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iowrite16be(val, &mod->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void ttl_setup_device(struct ttl_module *mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* reset the device to a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) iowrite16be(0x0000, &mod->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) iowrite16be(0x0001, &mod->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) iowrite16be(0x0000, &mod->regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* put all ports in open-drain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ttl_write_reg(mod, PORTA_IOCTL, 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ttl_write_reg(mod, PORTB_IOCTL, 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ttl_write_reg(mod, PORTC_IOCTL, 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* set all ports as outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ttl_write_reg(mod, PORTA_DIRECTION, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ttl_write_reg(mod, PORTB_DIRECTION, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ttl_write_reg(mod, PORTC_DIRECTION, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* set all ports to drive zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) iowrite16be(0x0000, &mod->regs->porta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) iowrite16be(0x0000, &mod->regs->portb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) iowrite16be(0x0000, &mod->regs->portc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* enable all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int ttl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct janz_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ttl_module *mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct gpio_chip *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mod = devm_kzalloc(&pdev->dev, sizeof(*mod), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) platform_set_drvdata(pdev, mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spin_lock_init(&mod->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* get access to the MODULbus registers for this module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mod->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (IS_ERR(mod->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return PTR_ERR(mod->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ttl_setup_device(mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Initialize the GPIO data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gpio = &mod->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) gpio->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gpio->label = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gpio->get = ttl_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gpio->set = ttl_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* request dynamic allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gpio->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) gpio->ngpio = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = devm_gpiochip_add_data(&pdev->dev, gpio, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(&pdev->dev, "unable to add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct platform_driver ttl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .probe = ttl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) module_platform_driver(ttl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_DESCRIPTION("Janz MODULbus VMOD-TTL Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_ALIAS("platform:janz-ttl");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags