^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // IXP4 GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // based on previous work and know-how from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Include that go away with DT transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip/irq-ixp4xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IXP4XX_REG_GPOUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IXP4XX_REG_GPOE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IXP4XX_REG_GPIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IXP4XX_REG_GPIS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IXP4XX_REG_GPIT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IXP4XX_REG_GPIT2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IXP4XX_REG_GPCLK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IXP4XX_REG_GPDBSEL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The hardware uses 3 bits to indicate interrupt "style".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * we clear and set these three bits accordingly. The lower 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * bits in two registers (GPIT1 and GPIT2) are used to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * the style for 8 lines each for a total of 16 GPIO lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IXP4XX_GPIO_STYLE_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * struct ixp4xx_gpio - IXP4 GPIO state container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @dev: containing device for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @fwnode: the fwnode for this GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @gc: gpiochip for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @base: remapped I/O-memory base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 0: level triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct ixp4xx_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long long irq_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void ixp4xx_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ixp4xx_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct ixp4xx_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ACK when unmasking if not edge-triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!(g->irq_edge & BIT(d->hwirq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ixp4xx_gpio_irq_ack(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ixp4xx_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int line = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 int_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) g->irq_edge |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) g->irq_edge |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) g->irq_edge |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) g->irq_edge &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) g->irq_edge &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (line >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* pins 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) line -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int_reg = IXP4XX_REG_GPIT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* pins 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int_reg = IXP4XX_REG_GPIT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_lock_irqsave(&g->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clear the style for the appropriate pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val = __raw_readl(g->base + int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __raw_writel(val, g->base + int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Set the new style */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = __raw_readl(g->base + int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __raw_writel(val, g->base + int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Force-configure this line as an input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val = __raw_readl(g->base + IXP4XX_REG_GPOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __raw_writel(val, g->base + IXP4XX_REG_GPOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* This parent only accept level high (asserted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct irq_chip ixp4xx_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "IXP4GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .irq_ack = ixp4xx_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .irq_unmask = ixp4xx_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .irq_set_type = ixp4xx_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int child_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int *parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* All these interrupts are level high in the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *parent_type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* GPIO lines 0..12 have dedicated IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (child == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *parent = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (child == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *parent = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (child >= 2 && child <= 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *parent = child + 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ixp4xx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct irq_domain *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct ixp4xx_gpio *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) g->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) g->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (IS_ERR(g->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return PTR_ERR(g->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * When we convert to device tree we will simply look up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * parent irqdomain using irq_find_host(parent) as parent comes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * the fwnode. For now we need this boardfile style code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device_node *irq_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq_parent = of_irq_find_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!irq_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "no IRQ parent node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) parent = irq_find_host(irq_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(dev, "no IRQ parent domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) g->fwnode = of_node_to_fwnode(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) parent = ixp4xx_get_irq_domain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) g->fwnode = irq_domain_alloc_fwnode(&res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!g->fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(dev, "no domain base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * specific machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (machine_is_dsmg600() || machine_is_nas100d())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * This is a very special big-endian ARM issue: when the IXP4xx is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * run in big endian mode, all registers in the machine are switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * around to the CPU-native endianness. As you see mostly in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * driver we use __raw_readl()/__raw_writel() to access the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * in the appropriate order. With the GPIO library we need to specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * byte order explicitly, so this flag needs to be set when compiling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * for big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #if defined(CONFIG_CPU_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Populate and register gpio chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = bgpio_init(&g->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) g->base + IXP4XX_REG_GPIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) g->base + IXP4XX_REG_GPOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) g->base + IXP4XX_REG_GPOE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(dev, "unable to init generic GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) g->gc.ngpio = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) g->gc.label = "IXP4XX_GPIO_CHIP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * TODO: when we have migrated to device tree and all GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * are fetched using phandles, set this to -1 to get rid of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * the fixed gpiochip base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) g->gc.base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) g->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) g->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) girq = &g->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) girq->chip = &ixp4xx_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) girq->fwnode = g->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) girq->parent_domain = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = devm_gpiochip_add_data(dev, &g->gc, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "failed to add SoC gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) platform_set_drvdata(pdev, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_info(dev, "IXP4 GPIO registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct of_device_id ixp4xx_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .compatible = "intel,ixp4xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct platform_driver ixp4xx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "ixp4xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .probe = ixp4xx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) builtin_platform_driver(ixp4xx_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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