^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO interface for IT87xx Super I/O chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on it87_wdt.c by Oliver Schuster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * gpio-it8761e.c by Denis Turischev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * gpio-stmpe.c by Rabin Vincent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Chip Id numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NO_DEV_ID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IT8613_ID 0x8613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IT8620_ID 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IT8628_ID 0x8628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IT8718_ID 0x8718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IT8728_ID 0x8728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IT8732_ID 0x8732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IT8761_ID 0x8761
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IT8772_ID 0x8772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IT8786_ID 0x8786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* IO Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VAL 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Logical device Numbers LDN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Configuration Registers and Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LDNREG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHIPID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHIPREV 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * struct it87_gpio - it87-specific GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @chip: the underlying gpio_chip structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @lock: a lock to avoid races between operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @io_base: base address for gpio ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @io_size: size of the port rage starting from io_base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @output_base: Super I/O register address for Output Enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @simple_base: Super I/O 'Simple I/O' Enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @simple_size: Super IO 'Simple I/O' Enable register size; this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * required because IT87xx chips might only provide Simple I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * switches on a subset of lines, whereas the others keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * same status all time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct it87_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 output_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 simple_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 simple_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct it87_gpio it87_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .lock = __SPIN_LOCK_UNLOCKED(it87_gpio_chip.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Superio chip access functions; copied from wdt_it87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline int superio_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Try to reserve REG and REG + 1 for exclusive access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) outb(0x87, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) outb(0x01, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) outb(0x55, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) outb(0x55, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void superio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) outb(0x02, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) outb(0x02, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) release_region(REG, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void superio_select(int ldn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) outb(LDNREG, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) outb(ldn, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline int superio_inb(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return inb(VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void superio_outb(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) outb(val, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline int superio_inw(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) outb(reg++, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val = inb(VAL) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val |= inb(VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void superio_outw(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) outb(reg++, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) outb(val >> 8, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) outb(reg, REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) outb(val, VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void superio_set_mask(int mask, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 curr_val = superio_inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 new_val = curr_val | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (curr_val != new_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) superio_outb(new_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void superio_clear_mask(int mask, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 curr_val = superio_inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 new_val = curr_val & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (curr_val != new_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) superio_outb(new_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 mask, group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mask = 1 << (gpio_num % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) group = (gpio_num / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_lock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* not all the IT87xx chips support Simple I/O and not all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * them allow all the lines to be set/unset to Simple I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (group < it87_gpio->simple_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) superio_set_mask(mask, group + it87_gpio->simple_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* clear output enable, setting the pin to input, as all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * newly-exported GPIO interfaces are set to input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) superio_clear_mask(mask, group + it87_gpio->output_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) spin_unlock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mask = 1 << (gpio_num % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = (gpio_num / 8) + it87_gpio->io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return !!(inb(reg) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 mask, group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mask = 1 << (gpio_num % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) group = (gpio_num / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* clear the output enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) superio_clear_mask(mask, group + it87_gpio->output_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_unlock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void it87_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned gpio_num, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 mask, curr_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mask = 1 << (gpio_num % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg = (gpio_num / 8) + it87_gpio->io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) curr_vals = inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) outb(curr_vals | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) outb(curr_vals & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int it87_gpio_direction_out(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned gpio_num, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 mask, group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct it87_gpio *it87_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mask = 1 << (gpio_num % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) group = (gpio_num / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_lock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* set the output enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) superio_set_mask(mask, group + it87_gpio->output_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) it87_gpio_set(chip, gpio_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock(&it87_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct gpio_chip it87_template_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .label = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .request = it87_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .get = it87_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .direction_input = it87_gpio_direction_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .set = it87_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .direction_output = it87_gpio_direction_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .base = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int __init it87_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int rc = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 chip_rev, gpio_ba_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) char *labels, **labels_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct it87_gpio *it87_gpio = &it87_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) chip_type = superio_inw(CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) chip_rev = superio_inb(CHIPREV) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) it87_gpio->chip = it87_template_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) switch (chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case IT8613_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gpio_ba_reg = 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) it87_gpio->io_size = 8; /* it8613 only needs 6, use 8 for alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) it87_gpio->output_base = 0xc8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) it87_gpio->simple_base = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) it87_gpio->simple_size = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) it87_gpio->chip.ngpio = 64; /* has 48, use 64 for convenient calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case IT8620_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case IT8628_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpio_ba_reg = 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) it87_gpio->io_size = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) it87_gpio->output_base = 0xc8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) it87_gpio->simple_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) it87_gpio->chip.ngpio = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case IT8718_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case IT8728_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case IT8732_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case IT8772_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case IT8786_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) gpio_ba_reg = 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) it87_gpio->io_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) it87_gpio->output_base = 0xc8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) it87_gpio->simple_base = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) it87_gpio->simple_size = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) it87_gpio->chip.ngpio = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case IT8761_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) gpio_ba_reg = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) it87_gpio->io_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) it87_gpio->output_base = 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) it87_gpio->simple_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) it87_gpio->chip.ngpio = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case NO_DEV_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_err("no device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_err("Unknown Chip found, Chip %04x Revision %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) chip_type, chip_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rc = superio_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) superio_select(GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* fetch GPIO base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) it87_gpio->io_base = superio_inw(gpio_ba_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) superio_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) chip_type, chip_rev, it87_gpio->chip.ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) it87_gpio->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) KBUILD_MODNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Set up aliases for the GPIO connection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * ITE documentation for recent chips such as the IT8728F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * refers to the GPIO lines as GPxy, with a coordinates system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * where x is the GPIO group (starting from 1) and y is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * bit within the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * By creating these aliases, we make it easier to understand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * to which GPIO pin we're referring to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!labels || !labels_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) goto labels_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) for (i = 0; i < it87_gpio->chip.ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) char *label = &labels[i * sizeof("it87_gpXY")];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sprintf(label, "it87_gp%u%u", 1+(i/8), i%8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) labels_table[i] = label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) it87_gpio->chip.names = (const char *const*)labels_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rc = gpiochip_add_data(&it87_gpio->chip, it87_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto labels_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) labels_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) kfree(labels_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) kfree(labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) release_region(it87_gpio->io_base, it87_gpio->io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void __exit it87_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct it87_gpio *it87_gpio = &it87_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gpiochip_remove(&it87_gpio->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) release_region(it87_gpio->io_base, it87_gpio->io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) kfree(it87_gpio->chip.names[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) kfree(it87_gpio->chip.names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) module_init(it87_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) module_exit(it87_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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